W83601R/G/W83602R/G

Publication Release Date: May 26, 2005

- 9 -

Revision 1.0

CR08 (GP Port 2: Input port Data Register, Default 0x--, Read Only)

This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is

defined as an input mode by CR0B. It will be inverted data by CR0A.

Bit 7: Reserved.

Bit 6 ~ 0: GP26 ~ GP20 Input Data Port.

CR09 (GP Port 2: Output port Data Register, Default 0x00, Read / Write)

This register is a data port for output only. It reflects the outgoing logic levels of the pins whether the pin

is defined as an output mode by CR0B. This register will reflect the value of output Flip-flop while read

access. The output data will be inverted or changed output style by CR0A or CR0C.

Bit 7: Reserved.

Bit 7 ~ 0: GP26 ~ GP20 Output Data Port.

CR0A (GP Port 2: Polarity Inversion Register, Default 0x70, Read / Write)

This register enables polarity inversion of pins defined as input or output by CR0B.

When set to a "1", the incoming/outgoing port value is inverted.

When set to a "0", the incoming/outgoing port value is the same as in data register.

Bit 7: Reserved.

Bit 6 ~ 0: GP26 ~ GP20 Polarity Inversion Register.

CR0B (GP Port 2: Input/Output Configuration Register, Default 0x7f, Read / Write)

This register selects Input or Output mode of pins.

When set to a "1", respective GPIO port is programmed as an input port.

When set to a "0", respective GPIO port is programmed as an output port.

Bit 7: Reserved.

Bit 6 ~ 0: GP26 ~ GP20 Input/Output Configuration Register.

CR0C (GP Port 2: Output Style Control Register, Default 0x00, Read / Write)

This register selects Output style of pins as level or pulse.

When set to a "1", respective GPIO port is programmed as a pulse signal.

When set to a "0", respective GPIO port is programmed as a level signal.

Bit 7: Reserved.

Bit 6 ~ 0: GP26 ~ GP20 Output Style Control Register.

CR0D (GP Port 2: Input latched data Register, Default 0x--, Read Only)

This register will latch Port 2 data while power on or RST# pin low, which is controlled by CR14h bit 1.

Bit 7: Reserved.

Bit 6 ~ 0: GP26 ~ GP20 Input latched data, which bit 2-0 are SMBus address bit A2-A0.

CR0E-0F Reserved Register