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PPC8572ECPXAULD Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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PPC8572ECPXAULD Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 140 page MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 3 Overview – Four inbound windows plus a default window on serial RapidIO™ – Four outbound windows plus default translation for PCI Express – Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support • Two 64-bit DDR2/DDR3 memory controllers — Programmable timing supporting DDR2 and DDR3 SDRAM — 64-bit data interface per controller — Four banks of memory supported, each up to 4 Gbytes, for a maximum of 16 Gbytes per controller — DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports — Full ECC support — Page mode support – Up to 32 simultaneous open pages for DDR2 or DDR3 — Contiguous or discontiguous memory mapping — Cache line, page, bank, and super-bank interleaving between memory controllers — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM — On-die termination support when using DDR2 or DDR3 — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access through JTAG port — 1.8-V SSTL_1.8 compatible I/O — Support 1.5-V operation for DDR3. The detail is TBD pending on official release of appropriate industry specifications. — Support for battery-backed main memory • Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture. — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts per processor with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters per processor that can generate interrupts — Supports a variety of other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing. |
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