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SI4432-B1 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI4432-B1 Datasheet(HTML) 5 Page - Silicon Laboratories |
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5 / 74 page  Si4430/31/32-B1 Rev 1.1 5 L IST OF F IGURES Figure 1. Si4430/31 RX/TX Direct-Tie Application Example .....................................................16 Figure 2. Si4432 Antenna Diversity Application Example .........................................................16 Figure 3. SPI Timing..................................................................................................................18 Figure 4. SPI Timing—READ Mode ..........................................................................................19 Figure 5. SPI Timing—Burst Write Mode ..................................................................................19 Figure 6. SPI Timing—Burst Read Mode ..................................................................................19 Figure 7. State Machine Diagram..............................................................................................20 Figure 8. TX Timing...................................................................................................................24 Figure 9. RX Timing ..................................................................................................................24 Figure 10. Frequency Deviation ................................................................................................28 Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................29 Figure 12. FSK vs GFSK Spectrums.........................................................................................32 Figure 13. Direct Synchronous Mode Example.........................................................................35 Figure 14. Direct Asynchronous Mode Example .......................................................................35 Figure 15. Microcontroller Connections.....................................................................................36 Figure 16. PLL Synthesizer Block Diagram...............................................................................38 Figure 17. FIFO Thresholds ......................................................................................................41 Figure 18. Packet Structure.......................................................................................................42 Figure 19. Multiple Packets in TX Packet Handler ....................................................................43 Figure 20. Required RX Packet Structure with Packet Handler Disabled .................................43 Figure 21. Multiple Packets in RX Packet Handler....................................................................43 Figure 22. Multiple Packets in RX with CRC or Header Error ...................................................44 Figure 23. Operation of Data Whitening, Manchester Encoding, and CRC ..............................46 Figure 24. Manchester Coding Example ...................................................................................46 Figure 25. Header .....................................................................................................................48 Figure 26. POR Glitch Parameters............................................................................................50 Figure 27. General Purpose ADC Architecture .........................................................................52 Figure 28. Temperature Ranges using ADC8 ...........................................................................54 Figure 29. WUT Interrupt and WUT Operation..........................................................................57 Figure 30. Low Duty Cycle Mode ..............................................................................................58 Figure 31. RSSI Value vs. Input Power.....................................................................................61 Figure 32. TX/RX Direct-Tie Reference Design—Schematic....................................................62 Figure 33. 20-Pin Quad Flat No-Lead (QFN) ............................................................................69 Figure 34. PCB Land Pattern ....................................................................................................70 |
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