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TEA152X Datasheet(PDF) 11 Page - NXP Semiconductors |
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TEA152X Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 20 page TEA152X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 14 September 2010 11 of 20 NXP Semiconductors TEA152x SMPS ICs for low-power systems Valley switching ( ΔV/Δt) vrec valley recognition voltage change with time −102 - +102 V/ μs fvalley ringing frequency for valley switching N × V o = 100 V 200 550 800 kHz td(vrec-swon) valley recognition to switch-on delay time -150 - ns Current and short-circuit winding protection Vsource(max) maximum voltage on pin SOURCE ΔV/Δt=0.1V/μs 0.470.500.53 V td(prop) delay from detecting Vsource(max) to switch-off ΔV/Δt=0.5V/μs - 160 185 ns Vswp short-winding protection voltage ΔV/Δt=0.5V/μs 0.7 0.75 0.8 V tleb leading edge blanking time 250 350 450 ns FET output stage IL(drain) leakage current on pin DRAIN Vdrain = 650 V - - 125 μA VBR(DRAIN) breakdown voltage on pin DRAIN Tj >0 °C 650 - - V RDSon drain-source on-state resistance TEA1520x Isource = −0.06 A Tj =25 °C - 48 55.2 Ω Tj =100 °C - 68 78.2 Ω TEA1521x Isource = −0.125 A Tj =25 °C - 24 27.6 Ω Tj =100 °C - 34 39.1 Ω TEA1522x Isource = −0.25 A Tj =25 °C - 12 13.8 Ω Tj =100 °C - 17 19.6 Ω TEA1523P Isource = −0.50 A Tj =25 °C- 6.5 7.5 Ω Tj =100 °C - 9.0 10.0 Ω tf(DRAIN) fall time on pin DRAIN Vi =300 V; no external capacitor at drain -75 - ns Temperature protection Tprot(max) maximum threshold temperature 150 160 170 °C Tprot(hys) hysteresis of protection temperature -2 - °C Table 6. Characteristics …continued Tamb =25 °C; no overtemperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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