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TLE7279-2GV50 Datasheet(PDF) 3 Page - Infineon Technologies AG |
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TLE7279-2GV50 Datasheet(HTML) 3 Page - Infineon Technologies AG |
3 / 24 page Data Sheet 3 Rev. 1.2, 2008-05-08 TLE7279-2 Pin Configuration 2 Pin Configuration 2.1 Pin Assignment (PG-DSO-14) Figure 1 Pin Configuration 2.2 Pin Definitions and Functions (PG-DSO-14) Pin Symbol Function 1RO Reset Output TLE7279-2GV33, TLE7279-2GV26: open drain output; TLE7279-2GV50: integrated 20 k Ω pull-up resistor; leave open if Reset is not needed 2-5, 10-12 GND Ground connect pin 2 and 3 to GND; connect pin 4-5, 10-12 to PCB heat sink area with GND potential 8SI Sense Input connect to Q if not needed 6RM Reset Mode power-on reset delay time selection: set to LOW for fast timing, to HIGH for slow timing; see reset timing definitions in “Electrical Characteristics” on Page 10; connect to Q or GND 7SO Sense Output TLE7279-2GV33, TLE7279-2GV26: open-drain output; TLE7279-2GV50: integrated 20 k Ω pull-up resistor; keep open, if sense comparator not needed 9Q Output Voltage block to GND with a ceramic capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in “Functional Range” on Page 7 13 I Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor 14 EN Enable Input low level disables the IC; integrated pull-down resistor to GND EN GND SO RM GND 8 SI 12 11 GND GND 1 2 3 4 5 GND 6 7 14 13 RO GND 9 10 AEP02113_7279 GND I Q |
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