ISL9305H

2

FN7724.0

November 8, 2010

Pin Configuration

ISL9305H

(16 LD 4X4 TQFN)

TOP VIEW

TABLE 1. TYPICAL APPLICATION PART LIST

PARTS

DESCRIPTION

MANUFACTURER

PART NUMBER

SPECIFICATIONS

SIZE

L1, L2

Inductor

Sumida

CDRH2D14NP-1R5

1.5µH/1.80A/50mΩ

3.0mmx3.0mmx1.55mm

C1

Input capacitor

Murata

GRM21BR60J106KE19L

10µF/6.3V

0805

C2, C3

Intput capacitor

Murata

GRM185R60J105KE26D

1µF/6.3V

0603

C4, C5

Output capacitor

Murata

GRM21BR71A106KE51L

10µF/6.3V

0805

C6, C7

Output capacitor

Murata

GRM185R60J105KE26D

1µF/6.3V

0603

R1, R2,

R3, R4

Resistor

Various

1%, SMD, 0.1W

0603

E-PAD

1

2

3

4

56

78

9

10

11

12

13

14

15

16

SCLK

VINDCD1

DCDPG

FB2

VINDCD2

FB1

SDAT

GNDLDO

Pin Descriptions

PIN NUMBER

(TQFN)

NAME

DESCRIPTION

1

VINDCD1

Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog

circuits.

2

FB1

Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For

fixed output versions, connect this pin directly to the DCD1 output.

3SCLK

4SDAT

5

VINLDO1

Input voltage for LDO1.

6VOLDO1

Output voltage of LDO1.

7VOLDO2

Output voltage of LDO2.

8

VINLDO2

Input voltage for LDO2.

9

GNDLDO

Power ground for LDO1 and LDO2.

10

DCDPG

The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1

and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter

voltages are within the power good range. The pin will be pulled low if either DCD is outside their range. When only

one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state

can be programmed for a delay of up to 200ms before being released to rise high. The programming range is