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ADC1410S065 Datasheet(PDF) 3 Page - NXP Semiconductors |
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ADC1410S065 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 35 page ADC1410S065_080_105_125_2 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 02 — 4 June 2009 3 of 35 NXP Semiconductors ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps 5. Block diagram Fig 4. Block diagram ADC1410S PGA SPI INTERFACE OUTPUT DRIVERS SYSTEM REFERENCE AND POWER MANAGEMENT ERROR CORRECTION AND DIGITAL PROCESSING ADC CORE 14-BIT PIPELINED T/H INPUT STAGE INP OTR PWD CMOS: D13 to D0 or LVDS/DDR: D13_M to D0_M D13_P to D0_P INM CLOCK INPUT STAGE AND DUTY CYCLE CONTROL 005aaa036 OE CMOS: DAV or LVDS/DDR: DAVP DAVM |
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