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ADC1410S080 Datasheet(PDF) 4 Page - NXP Semiconductors |
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ADC1410S080 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 35 page ADC1410S065_080_105_125_2 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 02 — 4 June 2009 4 of 35 NXP Semiconductors ADC1410S065/080/105/125 Single 14-bit ADC 65, 80, 105 or 125 Msps 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 5. Pin configuration with CMOS digital outputs selected Fig 6. Pin configuration with LVDS/DDR digital outputs selected ADC1410S HVQFN40 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VDDA INP INM AGND VDDA VCM AGND REFT REFB 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 AGND terminal 1 index area Transparent top view 005aaa037 ADC1410S HVQFN40 D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P VDDA INP INM AGND VDDA VCM AGND REFT REFB 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 AGND terminal 1 index area Transparent top view 005aaa038 Table 2. Pin description (CMOS digital outputs) Symbol Pin Type [2] Description REFB 1 O bottom reference REFT 2 O top reference AGND 3 G analog ground VCM 4 O common-mode output voltage VDDA 5 P analog power supply AGND 6 G analog ground INM 7 I complementary analog input INP 8 I analog input AGND 9 G analog ground VDDA 10 P analog power supply VDDA 11 P analog power supply CLKP 12 I clock input CLKM 13 I complementary clock input DEC 14 O regulator decoupling node OE 15 I output enable, active LOW PWD 16 I power down, active HIGH |
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