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CMX624 Datasheet(PDF) 8 Page - CML Microcircuits |
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CMX624 Datasheet(HTML) 8 Page - CML Microcircuits |
8 / 26 page V23 / Bell 202 Modem CMX624 2003 CML Microsystems Plc 8 D/624/7 1.5.4 FSK Demodulator This block is enabled when bits 1 and 5 of the FSK MODE Register are set to ‘1’, and converts the 75, 150 or 1200 bps FSK input signal to a binary received data signal which is sent to the Rx UART block. Note that in the absence of a valid FSK signal, the demodulator may falsely interpret speech or other extraneous signals as data. 1.5.5 Rx Energy and 2100Hz Detector The function of this block is controlled by Bits 4 and 5 of the FSK MODE Register and Bit 0 of the TX TONES Register. When Bit 0 of the TX TONES Register and Bits 4 and 5 of the FSK MODE Register are set to ‘1’ this block will measure the frequency and amplitude of the incoming signal. When a signal of 2100Hz is present of sufficient amplitude and time Bit 4 of the FLAGS Register is set high. See Section 1.7.1 for amplitude, time and frequency limits. When Bit 0 of the TX TONES Register is set to ‘0’ this block compares the level of the signal at the output of the Receive Filter against an internal threshold and may be used as a FSK level detector or a simple Call Progress Signal detector according to the settings of bits 4 and 5 of the FSK MODE Register, which affect the Receive Filter pass band as described in Section 1.5.3. The required register settings are summarised in the table below: TX TONES Reg FSK MODE Reg Bit 0 Bit 5 Bit 4 Detection Mode 0 0 0 Call Progress 0 1 0 75 / 150 bps FSK 0 1 1 1200 bps FSK 1 1 1 2100 Hz Bit 4 of the FLAGS Register is set to ‘1’ by the output of this block when the received level has exceeded the threshold for sufficient time. Amplitude and time hysteresis are used to reduce chattering in marginal conditions. See Section 1.7.1 for definitions of Teon and Teoff Figure 4 Rx Energy Detector Timing 1.5.6 FSK / DTMF Modulator When bit 7 of the TX TONES Register is set to ‘0’ then this block generates FSK signals as determined by bits 0 and 1 of the FSK MODE Register and the Tx data bits from the UART block as shown in the tables below: V.23 mode (bit 7 of SETUP register = ‘0’): FSK MODE Reg FSK / DTMF Modulator block output FSK Signal Frequency Bit 1 Bit 0 (Bit 7 of TX TONES = ‘0’) ‘0’ (Space) ‘1’ (Mark) 0 x Disabled (o/p held at VDD / 2) - - 1 0 75bps FSK 450Hz 390Hz 1 1 1200bps FSK 2100Hz 1300Hz |
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