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FAN5702UMP08X Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FAN5702UMP08X Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 17 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5702 • Rev. 1.0.3 10 I 2C Timing Specifications Guaranteed by design. Symbol Parameter Conditions Min. Typ. Max. Units fSCL SCL Clock Frequency Standard Mode 100 kHz Fast Mode 400 tBUF Bus-Free Time between STOP and START Conditions Standard mode 4.7 μs Fast Mode 1.3 tHD;STA START or Repeated START Hold Time Standard Mode 4 μs Fast Mode 600 ns tLOW SCL LOW Period Standard Mode 4.7 μs Fast Mode 1.3 ns tHIGH SCL HIGH Period Standard Mode 4 μs Fast Mode 600 ns tSU;STA Repeated START Setup Time Standard Mode 4.7 μs Fast Mode 600.0 ns tSU;DAT Data Setup Time Standard Mode 250 ns Fast Mode 100 ns tHD;DAT Data Hold Time Standard Mode 0 3.45 μs Fast Mode 0 900.00 ns tRCL SCL Rise Time Standard Mode 20+0.1CB 1000 ns Fast Mode 20+0.1CB 300 ns tFCL SCL Fall Time Standard Mode 20+0.1CB 300 ns Fast Mode 20+0.1CB 300 ns tRDA SDA Rise Time (6) Standard Mode 20+0.1CB 1000 ns Fast Mode 20+0.1CB 300 ns tFDA SDA Fall Time Standard Mode 20+0.1CB 300 ns Fast Mode 20+0.1CB 300 ns tSU;STO Stop Condition Setup Time Standard Mode 4 μs Fast Mode 600 ns CB Capacitive Load for SDA and SCL 400 pF Note: 6. Rise time of SCL after a repeated START condition and after an ACK bit. Timing Diagram START REPEATED START SCL SDA t F t HD;STA t LOW t R t HD;DAT t HIGH T SU;DAT t SU;STA t HD;STO t BUF START STOP t HD;STA Figure 18. I 2C Interface Timing for Fast and Slow Modes |
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