No. 6201-5/14

LB1876

Pin Description

Pin name

Pin number

Function

OUT1

2

OUT2

1

OUT3

36

IN1+, IN1–

8, 9

IN2+, IN2–

6, 7

IN3+, IN3–

4, 5

FG IN+

10

FG comparator non-inverting input.

FG IN–

11

FG comparator inverting input.

GND1

12

Control circuit ground.

GND2

13

Sub-ground.

PWM

14

PWM oscillation frequency setting pin. Connect to ground via capacitor.

FC

15

Current control circuit frequency characteristics compensation pin. Connect to ground via capacitor.

FGFIL

16

FG filter pin. Connect to ground via capacitor if noise in FG signal is a problem.

CSD

17

PH

18

RF waveform smoothing pin. Connect to ground via capacitor.

TOC

19

EO

20

Error amplifier output.

EI

21

Error amplifier input.

PD

22

Phase comparator output pin. Phase deviation is output as a duty cycle change of the pulse.

CLD

23

FGS

24

FG Schmitt output (open collector output).

LD

25

Phase lock detector output (open collector output). Goes ON when PLL is locked.

S/S

26

Start/stop input. Low: Start; High or Open: Stop.

CLK

27

Clock input. 10 kHz max.

VM1

28

Output block power supply. Short to VM2 for use.

VM2

29

VCC

30

Power supply pin. Connect to ground via capacitor to prevent noise.

VREG

31

5V regulator output pin (control circuit power supply). Connect to ground via capacitor to stabilize operation.

LDSEL

32

BRSEL

33

GND3

34

Output circuit ground.

FRAME

—

NC

3, 35

Not connected internally. Can be used for wiring.

Output pins.

PWM controls duty cycle ratio by lower transistors.

Connect Schottky diode between these pins and VCC.

Hall input pins for each phase.

Logic High indicates VIN+ > VIN–.

Restraint protection circuit operating time setting pin/reset pulse setting pin.

Connect to ground via capacitor. If the protection circuit is not to be used, connect a resistor in parallel

with capacitor.

Torque specifying input pin. Normally connected to EO pin. When TOC potential falls, ON duty cycle ratio of

lower side output transistors changes and torque increases.

Phase lock signal masking time setting pin. Connect to ground via capacitor. Leave open if masking is not

required.

Output current detector pin. Connect to VCC via low resistor.

Set to maximum output current IOUT = 0.5/Rf.

Phase lock signal masking switching pin. When "Low", the unlock signal (short "High" signal of LD output) is

masked. When "High" or Open, the lock signal (short "Low" signal of LD output) is masked.

Braking method select pin. "Low" selects reverse torque control and "High" or Open selects free-run.

When reverse torque is controlled, lower side output transistors require external SBD.

The FRAME pin is connected internally to the metal frame at the base of the IC. Electrically, both the FRAME

pin and the metal frame are left open. To improve thermal dissipation, provide a corresponding land on the

PCB and solder the FRAME pin to that land.