 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-BF561SKBCZ-6V Datasheet(PDF) 10 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-BF561SKBCZ-6V Datasheet(HTML) 10 Page - Analog Devices |
|
|
10 / 64 page  ADSP-BF561 • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable. The UART programmable features include: • Supporting bit rates ranging from (f SCLK/1,048,576) bits per second to (f SCLK/16) bits per second. • Supporting data formats from seven bits to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as: fSCLK UART Clock Rate = ----------------------------------------------- 16 × UART_Divisor Where the 16-bit UART_Divisor comes from the UART_DLH register (most significant 8 bits) and UART_DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA ®) serial infrared physi cal layer link specification (SIR) protocol. PROGRAMMABLE FLAGS (PFx) The ADSP-BF561 has 48 bidirectional, general-purpose I/O, programmable flag (PF47–0) pins. Some programmable flag pins are used by peripherals (see Pin Descriptions on Page 17). When not used as a peripheral pin, each programmable flag can be individually controlled by manipulation of the flag control, status, and interrupt registers as follows: • Flag direction control register – Specifies the direction of each individual PFx pin as input or output. • Flag control and status registers – Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a “write one to set” and “write one to clear” mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. Two control registers are provided, one register is written-to in order to set flag values, while another register is written-to in order to clear flag values. Reading the flag status register allows software to interro gate the sense of the flags. • Flag interrupt mask registers – These registers allow each individual PFx pin to function as an interrupt to the pro cessor. Similar to the flag control registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable an interrupt function, and the other flag interrupt mask register clears bits to disable an interrupt function. PFx pins defined as inputs can be con figured to generate hardware interrupts, while output PFx pins can be configured to generate software interrupts. • Flag interrupt sensitivity registers – These registers specify whether individual PFx pins are level- or edge-sensitive and specify, if edge-sensitive, whether just the rising edge or both the rising and falling edges of the signal are signifi cant. One register selects the type of sensitivity, and one register selects which edges are significant for edge sensitivity. PARALLEL PERIPHERAL INTERFACE The ADSP-BF561 processor provides two parallel peripheral interfaces (PPI0, PPI1) that can connect directly to parallel A/D and D/A converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates at up to f SCLK/2 MHz, and the synchronization signals can be configured as either inputs or outputs. The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bi-directional data transfer with up to 16 bits of data. Up to 3 frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex, bi-direc tional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported. General-Purpose Mode Descriptions The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: • Input mode – frame syncs and data are inputs into the PPI. • Frame capture mode – frame syncs are outputs from the PPI, but data are inputs. • Output mode – frame syncs and data are outputs from the PPI. Input Mode Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit, and 10-bit through 16-bit data, and are programmable in the PPI_CONTROL register. Rev. E | Page 10 of 64 | September 2009 |
Similar Part No. - ADSP-BF561SKBCZ-6V |
|
Similar Description - ADSP-BF561SKBCZ-6V |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
