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ADSP-BF533SBBZ500 Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-BF533SBBZ500 Datasheet(HTML) 2 Page - Analog Devices |
2 / 64 page Rev. H | Page 2 of 64 | January 2011 ADSP-BF531/ADSP-BF532/ADSP-BF533 TABLE OF CONTENTS General Description ................................................. 3 Portable Low Power Architecture ............................. 3 System Integration ................................................ 3 Processor Peripherals ............................................. 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Real-Time Clock ................................................... 8 Watchdog Timer .................................................. 9 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ....................... 10 UART Port ........................................................ 10 General-Purpose I/O Port F ................................... 10 Parallel Peripheral Interface ................................... 11 Dynamic Power Management ................................ 11 Voltage Regulation .............................................. 13 Clock Signals ..................................................... 13 Booting Modes ................................................... 14 Instruction Set Description ................................... 15 Development Tools ............................................. 15 Designing an Emulator-Compatible Processor Board .. 16 Related Documents .............................................. 17 Related Signal Chains ........................................... 17 Pin Descriptions .................................................... 18 Specifications ........................................................ 21 Operating Conditions ........................................... 21 Electrical Characteristics ....................................... 23 Absolute Maximum Ratings ................................... 26 ESD Sensitivity ................................................... 26 Package Information ............................................ 27 Timing Specifications ........................................... 28 Output Drive Currents ......................................... 44 Test Conditions .................................................. 46 Thermal Characteristics ........................................ 50 160-Ball CSP_BGA Ball Assignment ........................... 51 169-Ball PBGA Ball Assignment ................................. 54 176-Lead LQFP Pinout ............................................ 57 Outline Dimensions ................................................ 59 Surface-Mount Design .......................................... 62 Automotive Products .............................................. 63 Ordering Guide ..................................................... 64 REVISION HISTORY 1/11— Rev. G to Rev. H Corrected all document errata. Replaced Figure 7, Voltage Regulator Circuit ................ 13 Removed footnote 4 from VIL specifications in Operating Con- ditions ................................................................. 21 Changed Internal (Core) Supply Voltage (VDDINT) range in Absolute Maximum Ratings ..................................... 26, Replaced Figure 13, Asynchronous Memory Read Cycle Tim- ing ..................................................................... 29 Replaced Figure 14, Asynchronous Memory Write Cycle Tim- ing ..................................................................... 30 Replaced Figure 16, External Port Bus Request and Grant Cycle Timing ................................................................ 32 To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processor’s product page on the www.analog.com website and use the View PCN link. |
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