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LC651102N Datasheet(PDF) 4 Page - Sanyo Semicon Device |
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LC651102N Datasheet(HTML) 4 Page - Sanyo Semicon Device |
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4 / 19 page  No. 5221-4/19 LC65E1104 Pin Description Symbol Pins I/O Function Option At reset PROM mode • Address inputs A9 to A11 • EPROM control signal TA Identical to PE0 to PE1 Serial port: Disabled Interrupt source: INT Identical to PE0 to PE1 • I/O ports F0 tp F3 Identical to PE0 to PE1* • Shared with the serial interface and INT input. Program-selectable SI Serial input port SO Serial output port SCK Serial clock input/output INT Interrupt request input The serial I/O function can be switched between 4-bit and 8-bit operation under program control. Note: * No burst pulse output function is provided. I/O 4 PF0/SI/A9 PF1/SO/A10 PF2/SCK/A11 PF3/INT/TA • EPROM control signal CE • Address input A0 High-level output (Output Nch transistor: Off) 1. Open drain type output • I/O port: E0 and E1 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Setting or clearing in single-bit units (SPB, RPB instructions) Testing in single-bit units (BP and BNP instructions) • PE0 provides a continuous burst (64·Tcyc) function. I/O 2 PE0/CE PE1/WDR/A0 Data lines D4 to D7 Identical to PC0 to PC3 Identical to PC0 to PC3 I/O port: D0 to D3 Identical to PC0 to PC3 I/O 4 PD0/D4 PD1/D5 PD2/D6 PD3/D7 Data lines D0 to D3 • High-level output • Low-level output (Option-selectable) 1. Open drain type output 2. Output at reset: high 3. Output at reset: low 2., 3.: Specified in a group of 4 bits • I/O port: C0 to C3 Identical to PA0 to PA3* • Option permits output at reset to be high or low. Note: * No standby control function is provided. I/O 4 PC0/D0 PC1/D1 PC2/D2 PC3/D3 Address inputs A1 to A4 High-level output (Output Nch transistor: Off) Open drain type output • I/O port: A0 to A3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Testing in single-bit units (BP and BNP instructions) Setting or clearing in single-bit units (SPB and RPB instructions) • Standby is controlled by PA3 • The PA3 pin must be free from chattering during the halt instruction execution cycle. Each of these four pins has two functions as listed below. PA0/AD0: AD converter input pin AD0 PA1/AD1: AD converter input pin AD1 PA2/AD2: AD converter input pin AD2 PA3/AD3: AD converter input pin AD3 I/O 4 PA0/AD0/A1 PA1/AD1/A2 PA2/AD2/A3 PA3/AD3/A4 EPROM control signal DASEC — 1. Pin 2: RC oscillator external clock 2. Pin 2: Ceramic oscillator 3. Predivider option • No predivider • 1/3 predivider • 1/4 predivider • Connections for the external RC or ceramic oscillator circuit used as the system clock oscillator. • If external clock input is used, leave the OSC2 pin open. I O 1 1 OSC1/DASEC OSC2 — — — Power supply — — 1 1 VDD VSS Continued on next page. |
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