Low-Voltage, High-Accuracy, Quad Window

Voltage Detectors in Thin QFN

_______________________________________________________________________________________

7

Pin Description (continued)

PIN

NAME

FUNCTION

13

16

UVOUT2

Active-Low Undervoltage Output 2. When the voltage at UVIN2 falls below its threshold, UVOUT2

asserts low and stays asserted until the voltage at UVIN2 exceeds its threshold. The open-drain

14

17

OVOUT1

Active-Low Overvoltage Output 1. When the voltage at OVIN1 rises above its threshold, OVOUT1

asserts low and stays asserted until the voltage at OVIN1 falls below its threshold. The open-drain

15

18

UVOUT1

Active-Low Undervoltage Output 1. When the voltage at UVIN1 falls below its threshold, UVOUT1

asserts low and stays asserted until the voltage at UVIN1 exceeds its threshold. The open-drain

16

20

UVIN1

Undervoltage Threshold Input 1. When the voltage on UVIN1 falls below its threshold, UVOUT1

asserts low.

17

21

OVIN1

Overvoltage Threshold Input 1. When the voltage on OVIN1 rises above its threshold, OVOUT1

asserts low.

18

22

UVIN2

Undervoltage Threshold Input 2. When the voltages on UVIN2 falls below its threshold, UVOUT2

asserts low.

19

23

OVIN2

Overvoltage Threshold Input 2. When the voltage on OVIN2 rises above its threshold, OVOUT2

asserts low.

—

5

N.C.

Not Internally Connected

—12

MR

Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset

Ω resistor.

—

13

SRT

Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The

not set the reset timeout period to more than 1.12s. For the internal timeout period of 140ms (min),

—19

RESET

Active-Low Reset Output. RESET asserts low when the voltage on any of the UVIN_ inputs falls below

their respective thresholds, the voltage on any of the OVIN_ inputs goes above its respective

threshold, or MR is asserted. RESET remains asserted for at least the minimum reset timeout after all

monitored UVIN_ inputs exceed their respective thresholds, all OVIN_ inputs fall below their

respective thresholds, and MR is deasserted. This open-drain output has a 30µA internal pullup.

——

EP

Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low

thermal resistance path from the IC junction to the PC board. Do not use as the only electrical

connection to GND.