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SC4525D Datasheet(PDF) 10 Page - Semtech Corporation |
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SC4525D Datasheet(HTML) 10 Page - Semtech Corporation |
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10 / 21 page  © 2011 Semtech Corp. www.semtech.com SC4525D 10 Applications Information (Cont.) the regulator, the current-limit comparator ILIM (Figure 2) will eventually limit the switch current on a cycle-by- cycle basis. The over-current signal OC goes high, setting the latch B 3. The soft-start capacitor is discharged with (I D - IC) (Figure 3). If the inductor current falls below the current limit and the PWM comparator instead turns off the switch, then latch B 3 will be reset and IC will recharge the soft-start capacitor. If over-current condition persists or OC becomes asserted more often than PWM over a period of time, then the soft-start capacitor will be discharged below 1.9V. At this juncture, comparator B 4 sets the overload latch B 2. The soft-start capacitor will be continuously discharged with (I D - IC). The COMP pin is immediately pulled to ground. The switching regulator is shut off until the soft-start capacitor is discharged below 1.0V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through soft- start, overload shutdown and restart until it is no longer overloaded. If the FB voltage falls below 0.8V because of output overload, then the switching frequency will be reduced. Frequency foldback helps to limit the inductor current when the output is hard shorted to ground. During normal operation, the soft-start capacitor is charged to 2.4V. Setting the Output Voltage The regulator output voltage, V O, is set with an external resistive divider (Figure 1) with its center tap tied to the FB pin. For a given R 6 value, R4 can be found by (1) Minimum On Time Consideration The operating duty cycle of a non-synchronous step- down switching regulator in continuous-conduction mode (CCM) is given by (2) CESAT D IN D O V V V V V D − + + = − = 1 V 0 . 1 V R R O 6 4 1 SW D O L L F ) D 1 ( ) V V ( I ⋅ − ⋅ + = D SW O D O 1 F I % 20 ) D 1 ( ) V V ( L ⋅ ⋅ − ⋅ + = ) D 1 ( D I I O CIN _ RMS − ⋅ ⋅ = ⋅ ⋅ + ⋅ D = D O SW L O C F 8 1 ESR I V SW IN O IN F V 4 I C ⋅ D ⋅ > , R G R G S CA PWM ⋅ ≈ ) / s Q / s 1 () / s 1 ( ) C R s 1 ( G V V 2 n 2 n p O ESR PWM c o ω + ω + ω + + = 7 1 Z 5 R F 2 1 C π = 7 1 P 8 R F 2 1 C π = , C R 1 O p ≈ ω , C R 1 O ESR Z = ω k 3 . 22 10 28 . 0 10 R 3 7 20 9 . 15 = ⋅ = − nF 45 . 0 10 1 . 22 10 16 2 1 C 3 3 5 = ⋅ ⋅ ⋅ ⋅ π = pF 12 10 1 . 22 10 600 2 1 C 3 3 8 = ⋅ ⋅ ⋅ ⋅ π = ⋅ π ⋅ ⋅ − = O FB O C S CA C V V C F 2 1 R G 1 log 20 A dB 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 A 6 3 3 C = ⋅ ⋅ ⋅ ⋅ ⋅ π ⋅ ⋅ ⋅ ⋅ − = − − m 7 g 10 R 20 C A = CESAT D IN D O V V V V V D − + + = − = 1 V 0 . 1 V R R O 6 4 1 SW D O L L F ) D 1 ( ) V V ( I ⋅ − ⋅ + = D SW O D O 1 F I % 20 ) D 1 ( ) V V ( L ⋅ ⋅ − ⋅ + = ) D 1 ( D I I O CIN _ RMS − ⋅ ⋅ = ⋅ ⋅ + ⋅ D = D O SW L O C F 8 1 ESR I V SW IN O IN F V 4 I C ⋅ D ⋅ > , R G R G S CA PWM ⋅ ≈ ) / s Q / s 1 () / s 1 ( ) C R s 1 ( G V V 2 n 2 n p O ESR PWM c o ω + ω + ω + + = 7 1 Z 5 R F 2 1 C π = 7 1 P 8 R F 2 1 C π = , C R 1 O p ≈ ω , C R 1 O ESR Z = ω k 3 . 22 10 28 . 0 10 R 3 7 20 9 . 15 = ⋅ = − nF 45 . 0 10 1 . 22 10 16 2 1 C 3 3 5 = ⋅ ⋅ ⋅ ⋅ π = pF 12 10 1 . 22 10 600 2 1 C 3 3 8 = ⋅ ⋅ ⋅ ⋅ π = ⋅ π ⋅ ⋅ − = O FB O C S CA C V V C F 2 1 R G 1 log 20 A dB 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 A 6 3 3 C = ⋅ ⋅ ⋅ ⋅ ⋅ π ⋅ ⋅ ⋅ ⋅ − = − − m 7 g 10 R 20 C A = CESAT D IN D O V V V V V D − + + = − = 1 V 0 . 1 V R R O 6 4 1 SW D O L L F ) D 1 ( ) V V ( I ⋅ − ⋅ + = D SW O D O 1 F I % 20 ) D 1 ( ) V V ( L ⋅ ⋅ − ⋅ + = ) D 1 ( D I I O CIN _ RMS − ⋅ ⋅ = ⋅ ⋅ + ⋅ D = D O SW L O C F 8 1 ESR I V SW IN O IN F V 4 I C ⋅ D ⋅ > , R G R G S CA PWM ⋅ ≈ ) / s Q / s 1 () / s 1 ( ) C R s 1 ( G V V 2 n 2 n p O ESR PWM c o ω + ω + ω + + = 7 1 Z 5 R F 2 1 C π = 7 1 P 8 R F 2 1 C π = , C R 1 O p ≈ ω , C R 1 O ESR Z = ω k 3 . 22 10 28 . 0 10 R 3 7 20 9 . 15 = ⋅ = − nF 45 . 0 10 1 . 22 10 16 2 1 C 3 3 5 = ⋅ ⋅ ⋅ ⋅ π = pF 12 10 1 . 22 10 600 2 1 C 3 3 8 = ⋅ ⋅ ⋅ ⋅ π = ⋅ π ⋅ ⋅ − = O FB O C S CA C V V C F 2 1 R G 1 log 20 A dB 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 A 6 3 3 C = ⋅ ⋅ ⋅ ⋅ ⋅ π ⋅ ⋅ ⋅ ⋅ − = − − m 7 g 10 R 20 C A = CESAT D IN D O V V V V V D − + + = − = 1 V 0 . 1 V R R O 6 4 1 SW D O L L F ) D 1 ( ) V V ( I ⋅ − ⋅ + = D SW O D O 1 F I % 20 ) D 1 ( ) V V ( L ⋅ ⋅ − ⋅ + = ) D 1 ( D I I O CIN _ RMS − ⋅ ⋅ = ⋅ ⋅ + ⋅ D = D O SW L O C F 8 1 ESR I V SW IN O IN F V 4 I C ⋅ D ⋅ > , R G R G S CA PWM ⋅ ≈ ) / s Q / s 1 () / s 1 ( ) C R s 1 ( G V V 2 n 2 n p O ESR PWM c o ω + ω + ω + + = 7 1 Z 5 R F 2 1 C π = 7 1 P 8 R F 2 1 C π = , C R 1 O p ≈ ω , C R 1 O ESR Z = ω k 3 . 22 10 28 . 0 10 R 3 7 20 9 . 15 = ⋅ = − nF 45 . 0 10 1 . 22 10 16 2 1 C 3 3 5 = ⋅ ⋅ ⋅ ⋅ π = pF 12 10 1 . 22 10 600 2 1 C 3 3 8 = ⋅ ⋅ ⋅ ⋅ π = ⋅ π ⋅ ⋅ − = O FB O C S CA C V V C F 2 1 R G 1 log 20 A dB 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 A 6 3 3 C = ⋅ ⋅ ⋅ ⋅ ⋅ π ⋅ ⋅ ⋅ ⋅ − = − − m 7 g 10 R 20 C A = whereV IN is the input voltage, VCESAT is the switch saturation voltage, and V D is voltage drop across the rectifying diode. In peak current-mode control, the PWM modulating ramp is the sensed current ramp of the power switch. This current ramp is absent unless the switch is turned on. The intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse width. The propagation delay time required to immediately turn off the switch after it is turned on is the minimum controllable switch on time (T ON(MIN)). Closed-loop measurement shows that the SC4525D minimum on time is about 120ns at room temperature (Figure 4). If the required switch on time is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. Figure 4. Variation of Minimum On Time with Ambient Temperature To allow for transient headroom, the minimum operating switch on time should be at least 20% to 30% higher than the worst-case minimum on time. Minimum Off Time Limitation The PWM latch in Figure 2 is reset every cycle by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given 12 12 Fig.4: Min On-Time vs Temp Minumum On Time vs Temperature 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 Temperature (OC) SS270 REV 6-7 VO=1.5V, IO=1A 12 12 Fig.4: Min On-Time vs Temp Minumum On Time vs Temperature 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 Temperature (OC) SS270 REV 6-7 VO=1.5V, IO=1A |
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