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LC78602NE Datasheet(PDF) 6 Page - Sanyo Semicon Device |
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LC78602NE Datasheet(HTML) 6 Page - Sanyo Semicon Device |
6 / 11 page No. 6021-6/11 LC78602NE Pin Functions Pin No. Pin I/O Function Pin state during reset 1 DEFI I Defect detection signal (DEF) input. (Must be connected to 0 V if unused.) — 23 V/*5 V I Supply voltage selection input. (High: 3V operation, low: 5V operation) — 3 PDO O Internal VCO control phase comparator output Undefined 4VVSS — Internal VCO ground. This pin must be connected to 0 V. — 5 ISET AI PLL circuit pins PDO output current adjustment resistor connection — 6VVDD — Internal VCO power supply — 7 FR AI VCO frequency range adjustment — 8VSS — Digital system ground. This pin must be connected to 0 V. — 9 EFMO O Slice level EFM signal output Undefined 10 EFMIN I control pins EFM signal input — 11 TMOD I Test input. This pin must be connected to 0 V. — 12 CLV O Disc motor control output. This is a 3-value output. Hi-Z 13 HFL I Track detection signal input. This is a Schmitt input. — 14 TES I Tracking error signal input. This is a Schmitt input. — 15 TOFF O Tracking off output High output 16 TGL O Tracking gain switching output. A low level output raises the gain. Undefined 17 JP O Track jump control output. This is a 3-value output. Hi-Z 18 LASER O Laser control. A pull-down resistor is built in. Pulled down 19 FSTA O FSTA control. A pull-down resistor is built in. Pulled down 20 EFBAL O EFBAL control. A pull-down resistor is built in. Pulled down 21 SP8 O SP8 control. A pull-down resistor is built in. Pulled down 22 VDD — Digital system power supply — 23 FSEQ O Synchronizing signal detection output. Outputs a high level if the synchronizing signal detected Undefined from the EFM signal and the internally generated synchronizing signal match. EFM data playback clock monitor. 4.3218 MHz when the phase is locked. 24 PCK O (Note that this output is only provided in test mode. This pin outputs a low level during normal Low output mode operation.) 25 SLOF O Sled off control output High output 26 SLED+ O Sled feed output Low output 27 SLED– O Low output 28 PUIN I Limit switch detection input. A pull-up resistor is built in. — 29 DOUT O Digital output (EIAJ format) Undefined 30 NC — Unused pin. This pin must be left open. — 31 *SEG8 O Segment output (8). A pull-up resistor is built in. Pulled up 32 *SEG7 O Segment output (7). A pull-up resistor is built in. Pulled up 33 *SEG6 O Segment output (6). A pull-up resistor is built in. Pulled up 34 *SEG5 O Segment output (5). A pull-up resistor is built in. Pulled up 35 *SEG4 O Segment output (4). A pull-up resistor is built in. Pulled up 36 *SEG3 O Segment output (3). A pull-up resistor is built in. Pulled up 37 *SEG2 O Segment output (2). A pull-up resistor is built in. Pulled up 38 *SEG1 O Segment output (1). A pull-up resistor is built in. Pulled up 39 VSS — Digital system ground. This pin must be connected to 0 V. — 40 NC — Unused pin. This pin must be left open. — 41 *DIG2 O Common driver output (2). A pull-up resistor is built in. Pulled up 42 *DIG1 O Common driver output (1). A pull-up resistor is built in. Pulled up 43 *PROG O Program operation monitor. A pull-up resistor is built in. Pulled up 44 *KEYI1 I Key matrix input (1). A pull-up resistor is built in. — 45 NC — Unused pin. This pin must be left open. — 46 NC — Unused pin. This pin must be left open. — 47 *RANDOM O Random mode indicator output (Low: random mode, high: modes other than random mode.) Hi-Z Remote controller identifier input (3). This pin functions as an output pin set to the low level 48 RMTSL3 I/O during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin Low output switches to the high level. Therefore, applications that will set this pin high must connect an external pull-up resistor to this pin. Continued on next page. |
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