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K5N1229ACD-BQ12 Datasheet(PDF) 4 Page - Samsung semiconductor |
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K5N1229ACD-BQ12 Datasheet(HTML) 4 Page - Samsung semiconductor |
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4 / 128 page  - 4 - K5N1229ACD-BQ12 datasheet MCP Memory Rev. 1.0 2. General Description The K5N1229ACD is a Multi Chip Package Memory which combines 512Mb SLC MuxNOR Flash Memory and 128Mb Multiplexed Synchronous Burst Uni-Transistor Random Access Memory2. The 512Mb Muxed NOR Flash featuring single 1.8V power supply is a 512Mbit Muxed Burst Multi Bank Flash Memory organized as 32Mx16. The mem- ory architecture of the device is designed to divide its memory arrays into 512blocks(Uniform block part)/515 blocks(Boot block part) with independent hardware protection. This block architecture provides highly flexible erase and program capability. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the device(for 66/83MHz) pro- vides an 11ns burst access time and an 95ns initial access time at 66MHz. At 83MHz, the device(for 66/83MHz) provides an 9ns burst access time and an 95ns initial access time. At 108MHz, the device(for 108/133MHz) provides an 7ns burst access time and an 95ns initial access time. At 133MHz, the device(for 108/133MHz) provides an 6ns burst access time and an 95ns initial access time. The device performs a program operation in units of 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.6sec. The device requires 25mA as program/erase current in the extended temperature ranges. SAMSUNG’s UtRAM products are designed to meet the request from the customers who want to cope with the fast growing mobile applications that need high-speed random access memory. UtRAM is the solution for the mobile market with its low cost, high density and high performance feature. device is fabricated by SAMSUNG ′s advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous operation (asynchronous read and asynchronous write), the fully synchronous operation (synchronous burst read and synchronous burst write). These operation modes are defined through the configuration register setting. It supports the special features for the standby power saving. Those are the PAR(Partial Array Refresh) mode, and internal TCSR(Temperature Compensated Self Refresh). It also supports variable and fixed latency, driver strength settings, Burst sequence (wrap or No-wrap) options and a device ID register (DIDR). The K5N1229ACD is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 56-ball FBGA Type. |
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