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K6R4016C1D-EC0810 Datasheet(PDF) 8 Page - Samsung semiconductor

Part # K6R4016C1D-EC0810
Description  1Mx4 Bit High Speed Static RAM(5.0V Operating)
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

K6R4016C1D-EC0810 Datasheet(HTML) 8 Page - Samsung semiconductor

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K6R4004C1D
CMOS SRAM
PRELIMINARY
Rev. 2.0
- 8 -
July 2004
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
* X means Don
t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
LL
X
Write
DIN
ICC


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