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K6R4016C1D-EP0810 Datasheet(PDF) 3 Page - Samsung semiconductor |
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K6R4016C1D-EP0810 Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 9 page K6R4004C1D CMOS SRAM PRELIMINARY Rev. 2.0 - 3 - July 2004 1M x 4 Bit High-Speed CMOS Static RAM GENERAL DESCRIPTION FEATURES • Fast Access Time 10ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating K6R4004C1D-10 : 65mA(Max.) Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration K6R4004C1D-J : 32-SOJ-400 K6R4004C1D-K : 32-SOJ-400(Lead-Free) • Operating in Commercial and Industrial Temperature range. PIN FUNCTION Pin Name Pin Function A0 - A19 Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O4 Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection The K6R4004C1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 1,048,576 words by 4 bits. The K6R4004C1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG ′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4004C1D is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) SOJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O4 Vss Vcc I/O3 A14 A13 A12 A11 A10 N.C A0 A1 A2 A3 A4 CS I/O1 Vcc Vss I/O2 WE A5 A6 A7 A8 A9 Clk Gen. I/O1~I/O4 CS WE OE FUNCTIONAL BLOCK DIAGRAM Data Cont. Column Select CLK Gen. Pre-Charge Circuit Memory Array 1024 Rows 1024 x 4 Columns I/O Circuit A10 A12 A14 A16 A18 A11 A13 A15 A17 A19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 |
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Similar Description - K6R4016C1D-EP0810 |
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