TLV707 Series

SBVS153

– FEBRUARY 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

(2)

TLV707xx(x)Pyyyz

XX(X) is the nominal output voltage. For output voltages with a resolution of 100mV, two digits are used in the

ordering number; otherwise, three digits are used (for example, 18 = 1.8V, 285 = 2.85V).

P is optional; devices with P have an LDO regulator with an active output discharge.

YYY is the package designator.

Z is package quantity. Use R for reel (3000 pieces), and T for tape (250 pieces).

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2)

Output voltages from 1.2 V to 5.0 V in 50-mV increments are available. Contact factory for details and availability.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

MIN

MAX

UNIT

IN

–0.3

+6.0

V

EN

–0.3

+6.0

V

OUT

–0.3

+6.0

V

Current (source)

OUT

Internally limited

Output short-circuit duration

Indefinite

–55

+150

°C

Temperature

–55

+150

°C

Human body model (HBM) QSS 009-105 (JESD22-A114A)

2

kV

Electrostatic Discharge

Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)

500

V

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2)

All voltages are with respect to network ground terminal.

(3)

ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TLV707xx, TLV707xxP

DQN

DCK

UNITS

4 PINS

5 PINS

Junction-to-ambient thermal resistance

249.9

354.4

Junction-to-case (top) thermal resistance

N/A

108.2

Junction-to-board thermal resistance

N/A

136.5

°C/W

Junction-to-top characterization parameter

6.0

2.9

Junction-to-board characterization parameter

N/A

135.3

Junction-to-case (bottom) thermal resistance

N/A

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

DISSIPATION RATINGS

PACKAGE

DQN

249.9

°C/W

400 mW

220 mW

160 mW

DCK

354.4

°C/W

282 mW

155.2 mW

112.9 mW

2

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