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MPC5602DPB Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPC5602DPB Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 27 page Device family overview MPC5602D Microcontroller Product Brief, Rev. 3.1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 7 3.2 Critical performance parameters The critical performance parameters of the MPC5602D feature the following: • Fully static design operation up to a maximum of 48 MHz, based on 125 C ambient temperature • Low power design — Designed for dynamic power management of core and peripherals — Software-controlled clock gating of peripherals — Multiple power domains to minimize leakage in low power modes • Internal voltage regulator (VREG) enables control with a single input voltage for device operation below 100 mA with optional external ballast resistor for supporting maximum performance — 3.3 or 5 V ± 10% input supply voltage • ADC analog supply 3.3 or 5 V ± 10% • Configurable pins — Selectable pull-up, pull-down, or no pull on all GPIO pins — Selectable open-drain pin ADC 16 ch, 12-bit 33 ch, 12-bit 16 ch, 12-bit 33 ch, 12-bit CTU 16 ch Total timer I/O1 eMIOS 13 ch, 16-bit 28 ch, 16-bit 13 ch, 16-bit 28 ch, 16-bit • Type X2 2ch 5 ch 2ch 5 ch • Type Y3 —9 ch —9 ch • Type G4 7ch 7 ch 7ch 7 ch • Type H5 4ch 7 ch 4ch 7 ch SCI (LINFlex) 3 SPI (DSPI) 2 CAN (FlexCAN) 1 GPIO6 45 79 45 79 Debug JTAG Package 64 LQFP 100 LQFP 64 LQFP 100 LQFP NOTES: 1 Refer to eMIOS section of device reference manual for information on the channel configuration and functions. 2 Type X = MC + MCB + OPWMT + OPWMB + OPWFMB + SAIC + SAOC 3 Type Y = OPWMT + OPWMB + SAIC + SAOC 4 Type G = MCB + IPWM + IPM + DAOC + OPWMT + OPWMB + OPWFMB + OPWMCB + SAIC + SAOC 5 Type H = IPWM + IPM + DAOC + OPWMT + OPWMB + SAIC + SAOC 6 I/O count based on multiplexing with peripherals Table 2. MPC5602D device comparison (continued) Feature Device MPC5601DxLH MPC5601DxLL MPC5602DxLH MPC5602DxLL |
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