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AN-682 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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AN-682 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 3 page © 2001 Fairchild Semiconductor Corporation AN010644 www.fairchildsemi.com Fairchild Semiconductor Application Note July 1992 Revised November 2001 AN-682 Terminating F100K ECL Inputs Introduction Many F100K designs require that certain inputs be pre- sented with a HIGH or LOW level. Because of the con- struction of the F100K input circuitry, a LOW can be realized by simply leaving the input OPEN. However, a HIGH must be terminated in a special way. Simply tying the input to VCC/VCCA is unacceptable. Design Considerations The ranges of VIH and VIL across VEE (−4.2V to −5.7V for F100K ECL 300 Series) are −870 mV to −1165 mV and −1475 mV to −1830 mV respectively. By staying within these ranges, proper input conditions are assured. Figure 1 shows the voltage versus current for the F100K input tran- sistor. If the input is tied to VCC/VCCA the input transistor saturates (Point D) which can damage internal circuitry. The best VIH to realize a HIGH is a voltage drop of 0.9V below VCC/VCCA. As can be seen from the graph, this locates the quiescent point on the flat part of the curve (Point C) midway within the acceptable range of VIH. Fig- ure 2 shows three ways in which a HIGH can be realized on the input. These circuits allow the user to maintain con- stant input signals at optimum levels of VEE and tempera- ture. Each circuit can handle multiple fanouts, the number will depend upon the maximum current capability of the cir- cuit. The designer should be aware that although Figure 2A, Figure 2B, and Figure 2C supply ECL compatible sig- nals levels, they differ in power consumption and suscepti- bility to changes in temperature and VEE. For designs where there are multiple unused inputs and extra logic gates available, fanout from the unused gates is possible. As an example, one gate of the 100302 is capa- ble of driving ten quiescent inputs at voltage and current levels typical of F100K as shown in Figure 3. Figure 4 shows in detail the F100K pull-up scheme and the input circuitry. Although the circuits of Figure 2 are good examples, a detailed circuit analysis must include the 50 k Ω input resistor. In Figure 4A, the resistor (R D) which sets the diode biasing current is in parallel with the 50 k Ω input resistor. Similarly, the circuit of Figure 4B shows that R2 is in parallel with the input resistor. The point to emphasize is never tie an F100K input to VCC/ VCCA in order to realize a HIGH preset. Instead, the follow- ing is recommended: • For a LOW level — leave input open or tie to VEE. • For a HIGH level — tie input to a diode drop or 0.9V below VCC/VCCA. Remember also that the 50 k Ω input resistor must be con- sidered in the circuit parameter calculations. A = 50 KΩ Pull-Down Current B = Transition (Switching) Region C = Base Current plus 50 kΩ D = Input Transistor Saturation FIGURE 1. Input Characteristics |
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