Electronic Components Datasheet Search |
|
AN-684 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
|
AN-684 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 7 page 3 www.fairchildsemi.com TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES (Continued) Shift right/left modes are performed by making the appro- priate selection on the selection inputs (S2–S0). Each rising edge of the clock will cause the outputs to shift once in the direction which is selected. For shift-left operation, input D3 is used as the serial input. For shift-right operation, input CET/D0 is used as the serial input. During shift operation the terminal count output reflects the level at the Q3 output and the enables are “don't cares”. See Figure 3 for shift operation timing relationships and shift sequences. The 100336 provides two special modes of operation. The complement mode performs a one's complement of the outputs (Q3–Q 0) on the rising edge of the clock input regardless of the levels at the enable inputs. The hold fea- ture is asynchronous and simply stops counting or shifting operations. Both complement and hold are performed with proper selection of the select inputs. For a complete truth table of the 100336 operation, refer to Table 2. DESIGN CONSIDERATIONS Presetting the parallel inputs (P3–P 0) may require a mix- ture of HIGH's and LOW's. A LOW may be preset by leav- ing the respective input open as the 100336 has a 50 k Ω resistor to VEE on the parallel inputs. A HIGH must never be made by tying the input to VCC/VCCA. This saturates the input transistor. Instead the input is set at a diode drop below VCC/VCCA for a preset HIGH. See Applications Note 682. Unused output pairs (Qn/Qn) may be left unterminated. However, unused single outputs should be terminated to balance current switching in the outputs. For further details on system design considerations refer to the F100K ECL Design Guide. For AC/DC performance specifications and critical timing parameters refer to the 100336 datasheet. APPLICATIONS Figure 4 and Figure 5 demonstrate the use of the 100336 as UP/DOWN BCD counters. One additional gate is required to detect the limit count. Notice the alternate gate methods in Figure 4. The 100304 shows the classical AND/ NAND design similar to TTL and the 100302 shows the OR/NOR design of ECL. Figure 6 incorporates the use of a 100331 triple D-type flip- flop. By using one stage of the 100331, a 50/50 duty cycle can be realized from the divider. An 8-bit parallel-to-serial shifter can be constructed by cas- cading two 100336's as shown in Figure 7. The third counter reloads another 8-bit data word after eight serial counts. |
Similar Part No. - AN-684 |
|
Similar Description - AN-684 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |