3

www.fairchildsemi.com

Shift right/left modes are performed by making the appro-

edge of the clock will cause the outputs to shift once in the

is used as the serial input. For shift-right operation, input

and the enables are “don't cares”. See Figure 3 for shift

operation timing relationships and shift sequences.

The 100336 provides two special modes of operation. The

complement mode performs a one's complement of the

regardless of the levels at the enable inputs. The hold fea-

ture is asynchronous and simply stops counting or shifting

operations. Both complement and hold are performed with

proper selection of the select inputs. For a complete truth

table of the 100336 operation, refer to Table 2.

DESIGN CONSIDERATIONS

ture of HIGH's and LOW's. A LOW may be preset by leav-

ing the respective input open as the 100336 has a 50 k

Ω

input transistor. Instead the input is set at a diode drop

682.

However, unused single outputs should be terminated to

balance current switching in the outputs. For further details

on system design considerations refer to the F100K ECL

Design Guide. For AC/DC performance specifications and

critical timing parameters refer to the 100336 datasheet.

APPLICATIONS

Figure 4 and Figure 5 demonstrate the use of the 100336

as UP/DOWN BCD counters. One additional gate is

required to detect the limit count. Notice the alternate gate

methods in Figure 4. The 100304 shows the classical AND/

NAND design similar to TTL and the 100302 shows the

OR/NOR design of ECL.

Figure 6 incorporates the use of a 100331 triple D-type flip-

flop. By using one stage of the 100331, a 50/50 duty cycle

can be realized from the divider.

An 8-bit parallel-to-serial shifter can be constructed by cas-

cading two 100336's as shown in Figure 7. The third

counter reloads another 8-bit data word after eight serial

counts.