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AN4146 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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AN4146 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
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10 / 24 page  AN4146 APPLICATION NOTE 10 ©2005 Fairchild Semiconductor Corporation operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3, Dz and D1 from the feedback network. Thus, only Vo1 is regulated by the feedback circuit in normal operation and is determined as Figure 15 shows the standby mode operation waveforms. In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3, Dz and D1 to the reference pin of KA431. If R3 is much smaller than R1, Vo2 is dominant in the feedback loop. Before Vo2 drops to Vo2 stby, the voltage on the reference pin of KA431 is higher than 2.5V, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FPS and forces to stop switching. Once FPS stops switching, Vo2 decrease, and when Vo2 reaches Vo2 stby, the current through the opto LED decreases allowing the feedback voltage to rise. When the feedback voltage reaches 0.4V, FPS resumes switching with a predetermined peak drain current. Assuming that the forward voltage drop of D1 is 0.5V, the approximate output voltage for Vo2 in standby mode is given by where VZB is the zener breakdown voltage of Dz. Figure 15. Burst Operation Waveforms [STEP-14] Design the feedback control circuit. Since FSCQ-series employs current mode control as shown in Figure 16, the feedback loop can be easily implemented with a one-pole and one-zero compensation circuit. The current control factor of FPS, K is defined as where Ipk is the peak drain current and VFB is the feedback voltage for a given operating condition, ILIM is the current limit of the FPS and VFBsat is the internal feedback saturation voltage, which is typically 2.5V. Figure 16. Control Block Diagram For quasi-resonant flyback converter, the control-to-output transfer function using current mode control is given by where VDC is the DC input voltage, RL is the effective total load resistance of the controlled output, which is defined as Vo1 2/P o , Np and Ns1 are specified in STEP-7, VRO is specified in STEP-3, Vo1 is the reference output voltage, Po is specified in STEP-1 and K is specified in equation (38). The pole and zeros of equation (39) are defined as where Lm is specified in equation (7), D is the duty cycle of V o1 2.5 R 1 R 2 + R2 -------------------- ⎝⎠ ⎛⎞ ⋅ = (36) V 02 stby V ZB 0.5 2.5 ++ = (37) V o2 V o2 stby V FB 0.4V Standby mode Normal mode I ds K I pk V FB ---------- I LIM V FBsat ----------------- = = (38) . ˆ ˆ 1 o FB v and v In order to express the small signal AC transfer functions, the small signal variations of feedback voltage (v FB) and controlled output voltage (v o1) are introduced as v o1 R D i D R bias R 1 R 2 i bias C B v FB CTR :1 FPS v bias C F R F KA431 I pk MOSFET current R B G vc vˆo1 vˆFB --------- = KR LVDC Np Ns1 ⁄ () ⋅ 22V RO v DC + () ----------------------------------------------------- 1s +w z ⁄ () 1s – w rz ⁄ () 1s +w p ⁄ ---------------------------------------------------------- ⋅ =39 () w z 1 R c1Co1 --------------------, w rz R L 1D – () 2 DL m Ns1 Np ⁄ () 2 ----------------------------------------- and w p 1D + () R LCo1 ------------------- == = |
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