AN-9719

APPLICATION NOTE

© 2010 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.0 • 11/2/10

9

One simple and practical way to address this problem is

designing the feedback loop for low input voltage and full-

load condition with enough phase and gain margin. When

the converter operates in CCM, the RHP zero is lowest in

low input voltage and full-load condition. The gain

increases only about 6dB as the operating condition is

changed from the lowest input voltage to the highest input

voltage condition under universal input condition. When the

operating mode changes from CCM to DCM, the RHP zero

disappears, making the system stable. Therefore, by

designing the feedback loop with more than 45 degrees of

phase margin in low input voltage and full-load condition,

the stability over all the operating ranges can be guaranteed.

Figure 15 is a typical feedback circuit mainly consisting of a

for control-loop compensation. The maximum source

current of the FB pin is about 1mA. The phototransistor

must be capable of sinking this current to pull the FB level

·

(23)

KA431 (2.5V); and CTR is the current transfer rate of the

opto-coupler.

6V

+

-

Figure 15. Feedback Circuit

The feedback compensation network transfer function of

Figure 15 is obtained as:

·

1

⁄

1

⁄

(24)

where

,

1

1

(25)

(Design Example)

Assuming CTR is 100%,

·

1 10

110

12

1.2

2.5

110

8.3 Ω

The minimum cathode current for KA431 is 1mA.

1.2 Ω.

1k

designed to provide 2.5V to the reference pin of the

2.5 ·

2.5

2.5 ·

12

2.5

3.8

38.2k

[STEP-11] Design Input Voltage Sensing Circuit

Figure 16 shows a resistive voltage divider with low-pass

filter for line-voltage detection of the VIN pin. FSL-series

voltage reaches 1.03V. If latch protection is triggered, the

voltage drops below 0.7V. It is typical to use 100:1 voltage

Figure 16. Input Voltage Sensing