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v1.1
© 2008–2011 Teridian Semiconductor Corporation
9
IAP
MUX
and
PREAMP
XIN
XOUT
VREF
CKADC
CE
32-bit Compute
Engine
MPU
(80515)
CE CONTROL
OPT_RX/
SEGDIO55
OPT_TX/
SEGDIO51/
WPULSE/
VARPULSE
RESET
VBIAS
EMULATOR
PORT
3
OPTICAL
INTERFACE
UART0
TX
RX
6
COM0..5
VLC2
LCD DRIVER
CEDATA
0x000...0x2FF
PROG
0x000...0x3FF
DATA
0x0000...0xFFFF
PROGRAM
0x0000...0xFFFF
0x0000…
0xFFFF
DIGITAL I/O
CONFIGURATION
RAM
(I/O RAM)
0x2000...0x20FF
MEMORY SHARE
0x0000...0x13FF
16
8
RTCLK
RTCLK (32KHz)
MUX_SYNC
CKCE
CKMPU
CK32
32
8
8
8
POWER FAULT
DETECTION
4.9 MHZ
< 4.9MHz
4.9 MHz
GNDD
V3P3A
V3P3D
VBAT
Voltage
Regulator
2.5V to logic
VDD
32KHz
MPU_RSTZ
FAULTZ
WAKE
CON-
FIGURATION
PARAMETERS
GNDA
VBIAS
2/15/2011
CROSS
CLOCK GEN
Oscillator
32 KHz
CK32
MCK
PLL
VREF
DIV
ADC
MUX CTRL
STRT
MUX
MUX
CKFIR
RTM
SEGDIO Pins
WPULSE
VARPULSE
WPULSE
VARPULSE
TEST
TEST
MODE
VLC1
VLC0
< 4.9MHz
CKMPU_2x
CKMPU_2x
SDCK
SDOUT
SDIN
E_RXTX/SEG48
E_TCLK/SEG49
E_RST/SEG50
FLASH
64/32 KB
V3P3A
FIR
EEPROM
INTERFACE
CK_4X
LCD_GEN
PB
RTC
VBIAS
MEMORY
SHARE
16
E_RXTX
E_TCLK
E_RST(Open Drain)
ICE_E
∆Σ
AD CONVERTER
+
-
VREF
V3P3SYS
TEST MUX
VLCD
VLCD
Voltage
Boost
MPU RAM
3/5 KB
22
VSTAT
VBAT_RTC
IAN
IBP
IBN
VA
VB*
SEG Pins
2
TEST MUX
2
Non-Volatile
CONFIGURATION
RAM
BAT
TEST
TEMP
SENSOR
RTM
* 71M6542 only
Figure 1: IC Functional Block Diagram
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