TB62777FNG/FG

2010-03-08

3

Timing Diagram

Note 1: Latches are level-sensitive, not edge-triggered.

voltage.

Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK.

Marks:

The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the

latches do not hold data and pass it transparently. When the

ENABLE terminal is Low, OUT0 to OUT7

toggle between ON and OFF according to the data. When the ENABLE terminal is High, OUT0 to

OUT7 are forced OFF.

SERIAL-IN

LATCH

CLOCK

OUT0

OUT1

SERIAL-OUT

ENABLE

OUT7

H

L

n

= 0

1

2

345

67

H

L

H

L

H

L

ON

OFF

ON

OFF

ON

OFF

ON

OFF

H

L

Data applied when n

= 0

2

OUT