STK672-040

No. 5227—5/11

Design material

1. Explanation of input pins

2. Functions and timing of input signals

2-1. CLK (Phase switching clock)

1. Input frequency range

sDC to 50 kHz

2. Minimum pulse width

s10

µs

3. Duty

s40 to 60%

4. Pin format

sCMOS Schmitt containing pull-up resistor (20 k

Ω typical value)

5. Noise eliminating circuit with multiple stages is contained.

6. Functions

a. When the signal M3 is set to 1 or it is opened.

The exciting phase moves at each step at the leading edge of the clock.

b. When the signal M3 is set to 0

The exciting phase moves at each step at the leading and trailing edges of the clock.

2-2. CWB (Setting of rotation direction)

1. Pin format

sCMOS Schmitt configuration containing pull-up resistor

(20k

Ω, typical value)

2. Function

a. When the signal CWB is set to 1

It rotates clockwise.

b. When the signal CWB is set to 0

It rotates counterclockwise.

3. Note

sWhen the signal M3 is set to 0, the CWB input signal must not be changed

at the leading edge and trailing edge of the clock input for the period of 5

µs.

Pin No.

Name

Function

Pin format

14

CLK

Phase switching phase

CMOS Schmitt configuration with pull-down resistor

15

CWB

Setting of rotation direction (CW/CCW)

CMOS Schmitt configuration with pull-down resistor

17

RETURN

Phase origin forced return

CMOS Schmitt configuration with pull-down resistor

18

ENABLE

Output cut-off

CMOS Schmitt configuration with pull-down resistor

9, 10, 11

M1, M2, M3

Setting of exciting mode

CMOS Schmitt configuration with pull-down resistor

12, 13

M4, M5

Setting of vector locus

CMOS Schmitt configuration with pull-down resistor

16

RESET

System reset

CMOS Schmitt configuration with pull-down resistor

8

Vref

Setting of current value

CMOS Schmitt configuration with pull-down resistor