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I.MX27 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 152 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.7 Freescale Semiconductor 23 Functional Description and Application Information and reception. It also has programmable data interface modes such as I2S, LSB, and MSB aligned and programmable word lengths. Other program options include frame sync, clock generation, and programmable I2S modes (Master, Slave, or Normal). Oversampling clock, ccm_ssi_clk is available as output from SRCK in I2S Master mode. In addition to AC97 support, the SSI has completely separate clock and frame sync selections for the receive and transmit sections. In the AC97 standard, the clock is taken from an external source and frame sync is generated internally. The SSI also has a programmable internal clock divider and Time Slot Mask registers for reduced CPU overhead (for Tx and RX both). 2.3.35 Universal Asynchronous Receiver/Transmitter (UART) The i.MX27/MX27L processors contain six UART modules. Each UART module is capable of standard RS-232 non-return-to-zero (NRZ) encoding format and IrDA-compatible infrared modes. The UART provides serial communication capability with external devices through an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception); or it transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low-speed IrDA compatibility. The UART transmits and receives characters that are either 7 or 8 bits in length (program selectable). To transmit, data is written from the peripheral data bus to a 32-byte transmitter FIFO (TxFIFO). This data is passed to the shift register and shifted serially out on the transmitter pin (TXD). To receive, data is received serially from the receiver pin (RXD) and stored in a 32-half-word-deep receiver FIFO (RxFIFO). The received data is retrieved from the RxFIFO on the peripheral data bus. The RxFIFO and TxFIFO generate maskable interrupts as well as DMA requests when the data level in each of the FIFO reaches a programmed threshold level. The UART generates baud rates based on a programmable divisor and input clock. The UART also contains programmable auto baud detection circuitry to receive 1 or 2 stop bits as well as odd, even, or no parity. The receiver detects framing errors, idle conditions, BREAK characters, parity errors, and overrun errors. 2.3.36 Universal Serial Bus (USB) The i.MX27/MX27L processors provide three USB ports. The USB module provides high performance USB On-The-Go (OTG) functionality, compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 Low Pin Count specification. The module consists of three independent USB cores, each controlling one USB port. In addition to the USB cores, the USB module provides for Transceiverless Link (TLL) operation on host Ports 1 and 2, and provides the ability of routing the OTG transceiver interface to Host Port 1 such that this transceiver can be used to communicate with a USB peripheral connected to Host Port 1. The USB module has two connections to the CPU bus—one IP-bus connection for register accesses and one AHB-bus connection for the DMA transfer of data to and from the FIFOs. The USB module includes the following features: • Full Speed/Low speed Host only core (HOST 1) • Transceiverless Link Logic (TLL) for on board connection to a FS/LS USB peripheral |
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