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I.MX27 Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 152 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.7 86 Freescale Semiconductor Electrical Characteristics • All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. • All timings are on AUDMUX pads when SSI is being used for data transfer. • “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. • For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data (for example, during AC97 mode of operation). 4.3.11.2 SSI Receiver Timing with Internal Clock Figure 47 and Figure 48 show the SSI receiver timing with internal clock, and Table 47 lists the timing parameters. Figure 47. SSI Receiver with Internal Clock Timing Diagram Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling 10.0 — ns SS43 SRXD hold after (Tx) CK falling 0 — ns SS52 Loading — 25 pF Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued) ID Parameter Min Max Unit SS50 SS48 AD1_TXC AD1_TXFS (bl) AD1_TXFS (wl) AD1_RXD AD1_RXC SS1 SS4 SS2 SS51 SS20 SS21 SS49 SS7 SS9 SS11 SS13 SS47 (Output) (Output) (Output) (Input) (Output) SS3 SS5 |
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