SKYPER™ 32PRO R

11

2007-01-19 – Rev03

© by SEMIKRON

Halt Logic Signal (HLS)

The Halt Logic Signals PRIM_HALT_IN and PRIM_HALT_OUT show and control the drive core status. The driver core is

placed into halt mode by setting PRIM_HALT_IN into HIGH state (disable driver). This signal can gather disable signals of

other hardware components for stopping operation and switching off the IGBT. A HIGH signal will set the driver core into

HOLD and switching pulses from the controller will be not transferred to the output stage. The input and output have Schmitt

Trigger characteristic. Pull up and open collector output stages must not be used.

Connection PRIM_HALT_OUT and PRIM_HALT_IN

Connection PRIM_HALT_OUT (PRIM_HALT_IN not used)

Dead Time generation (Interlock TOP / BOT) adjustable (DT)

The DT circuit prevents, that TOP and BOT IGBT of one half bridge are switched on at the same time (shoot through). The

dead time is not added to a dead time given by the controller. Thus the total dead time is the maximum of "built in dead time"

and "controller dead time". It is possible to control the driver with one switching signal and its inverted signal.

Pulse pattern – DT

The total propagation delay of the driver is the sum of interlock

time of the IGBT chip has to be taken into account (not shown in

the pulse pattern).

In

case

both

channel

inputs

(PRIM_TOP_IN

and

PRIM_BOT_IN) are at high level, the IGBTs will be turned off.

If only one channel is switching, there will be no interlock dead

time.

The dead time can be adjusted and the locking function may be neutralized as shown in the following table.

Please note:

No error message will be generated when overlap of switching signals occurs.

Please note:

A HIGH signal @ PRIM_HALT_IN does not generate a HIGH signal @ PRIM_HALT_OUT. After LOW signal @ PRIM_HALT_IN the

gate driver is enable do operate.

Please note:

PRIM_HALT_OUT must be always connected with PRIM_HALT_IN. PRIM_HALT_OUT is not short circuit proof.