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AD5755 Datasheet(PDF) 11 Page - Analog Devices |
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AD5755 Datasheet(HTML) 11 Page - Analog Devices |
11 / 48 page AD5755 Rev. 0 | Page 11 of 48 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Parameter Rating AVDD, VBOOST_x to AGND, DGND −0.3 V to +33 V AVSS to AGND, DGND +0.3 V to −28 V AVDD to AVSS −0.3 V to +60 V AVCC to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) Digital Outputs to DGND −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) REFIN, REFOUT to AGND −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) VOUT_x to AGND AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry +VSENSE_x, −VSENSE_x to AGND AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry IOUT_x to AGND AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry SWx to AGND −0.3 to +33 V AGND, GNDSWx to DGND −0.3 V to +0.3 V Operating Temperature Range (TA) Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 64-Lead LFCSP θJA Thermal Impedance2 20°C/W Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD CAUTION 1 Power dissipated on chip must be derated to keep the junction temperature below 125°C. 2 Based on a JEDEC 4-layer test board. |
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Similar Description - AD5755_11 |
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