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AD6641-500EBZ Datasheet(PDF) 7 Page - Analog Devices |
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AD6641-500EBZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 28 page AD6641 Rev. 0 | Page 7 of 28 AD6641-500 Parameter1 Temp Min Typ Max Unit LOGIC OUTPUTS DDR LVDS Mode (PCLK±, PD[5:0]±, PDOR±) Logic Compliance Full LVDS VOD Differential Output Voltage Full 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 V Parallel CMOS Mode (PCLK±, PD[11:0]) Logic Compliance Full CMOS High Level Output Voltage Full DRVDD − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 5 pF loading. SWITCHING SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 4. AD6641-500 Parameter1 Temp Min Typ Max Unit OUTPUT DATA RATE Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, Parallel CMOS or DDR LVDS Mode Interface) Full 62.5 MHz Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, SPORT Mode) Full 62.5 MHz PULSE WIDTH/PERIOD (CLK±) CLK± Pulse Width High (tCH) Full 1 ns CLK± Pulse Width Low (tCL) Full 1 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns PULSE WIDTH/PERIOD (PCLK±, DDR LVDS MODE) PCLK± Pulse Width High (tPCLK_CH) Full 8 ns PCLK± Period (tPCLK) Full 16 ns Propagation Delay (tCPD, CLK± to PCLK±) Full ±0.1 ns Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns Data to PCLK Skew (tSKEW) Full 0.2 ns SERIAL PORT OUTPUT TIMING2 SP_SDFS Propagation Delay (tDSDFS) Full 3 ns SP_SDO Propagation Delay (tDSDO) Full 3 ns SERIAL PORT INPUT TIMING SP_SDFS Setup Time (tSSF) Full 2 ns SP_SDFS Hold Time (tHSF) Full 2 ns FILL± INPUT TIMING FILL± Setup Time (tSfill) Full 0.5 ns FILL± Hold Time (tHfill) Full 0.7 ns APERTURE DELAY (tA) 25°C 0.85 ns APERTURE UNCERTAINTY (JITTER, tJ) 25°C 80 fs rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 5 pF loading. |
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