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MC68EN360FE25V Datasheet(PDF) 7 Page - Motorola, Inc |
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MC68EN360FE25V Datasheet(HTML) 7 Page - Motorola, Inc |
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7 / 962 page  Table of Contents Paragraph Title Page Number Number MOTOROLA MC68360 USER’S MANUAL iii QUICC Memory Map 3.1 Dual-Port RAM Memory Map .................................................................. 3-2 3.2 CPM Sub-Module Base Addresses......................................................... 3-3 3.3 Internal Registers Memory Map .............................................................. 3-4 3.3.1 SIM Registers Memory Map.................................................................... 3-4 3.3.2 CPM Registers Memory Map .................................................................. 3-6 Section 4 Bus Operation 4.1 Bus Transfer Signals ............................................................................... 4-2 4.1.1 Bus Control Signals................................................................................. 4-3 4.1.2 Function Codes (FC3–FC0) .................................................................... 4-3 4.1.3 Address Bus (A31–A0)............................................................................ 4-4 4.1.4 Address Strobe (AS) ............................................................................... 4-4 4.1.5 Data Bus (D31-D0).................................................................................. 4-4 4.1.6 Data Strobe (DS)..................................................................................... 4-4 4.1.7 Output Enable (OE)................................................................................. 4-4 4.1.8 Byte Write Enable (WE0, WE1, WE2, WE3) ........................................... 4-4 4.1.9 Bus Cycle Termination Signals ............................................................... 4-5 4.1.9.1 Data transfer and size acknowledge (DSACK1 and DSACK0). .............. 4-5 4.1.9.2 Bus Error (BERR).................................................................................... 4-5 4.1.9.3 Autovector (AVEC). ................................................................................. 4-6 4.2 Data Transfer Mechanism ....................................................................... 4-6 4.2.1 Dynamic Bus Sizing ................................................................................ 4-6 4.2.2 Misaligned Operands ............................................................................ 4-11 4.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment .................. 4-19 4.2.4 Bus Operation ....................................................................................... 4-20 4.2.5 Synchronous Operation with DSACKx .................................................. 4-21 4.2.6 Fast Termination Cycles........................................................................ 4-21 4.3 Data Transfer Cycles............................................................................. 4-22 4.3.1 Read Cycle............................................................................................ 4-23 4.3.2 Write Cycle ............................................................................................ 4-26 4.3.3 Read-Modify-Write Cycle ...................................................................... 4-28 4.4 CPU Space Cycles................................................................................ 4-31 4.4.1 Breakpoint Acknowledge Cycle............................................................. 4-31 4.4.2 LPSTOP Broadcast Cycle ..................................................................... 4-35 4.4.3 Module Base Address Register (MBAR) Access .................................. 4-36 4.4.4 Interrupt Acknowledge Bus Cycles........................................................ 4-36 4.4.4.1 Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36 4.4.4.2 Autovector Interrupt Acknowledge Cycle. ............................................. 4-38 4.4.4.3 Spurious Interrupt Cycle........................................................................ 4-40 4.5 Bus Exception Control Cycles ............................................................... 4-41 4.5.1 Bus Errors ............................................................................................. 4-42 4.5.2 Retry Operation ..................................................................................... 4-44 4.5.3 Halt Operation ....................................................................................... 4-46 4.5.4 Double Bus Fault................................................................................... 4-48 |
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