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BQ77910DBTR Datasheet(PDF) 2 Page - Texas Instruments |
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BQ77910DBTR Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 56 page  bq77910 SLUSA07B – AUGUST 2010 – REVISED MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN DETAILS PIN FUNCTIONS (38-Pin Package) PIN DESCRIPTION NAME NO. BAT 31 Power supply voltage, tied to highest cell(+) CCAP 20 Energy storage capacitor for charge FET drive CHG 21 Charge FET (n-channel) gate drive CHGST 14 Charger-status input, used to detect charger connection/wakeup CPCKN 19 Pack – charger negative terminal (charger return) DCAP 16 Energy storage capacitor for discharge FET drive DPCKN 18 Pack – discharge negative terminal (load return) DSG 17 Discharge FET (n-channel) gate drive EEPROM 28 EEPROM programming voltage input. Connect to VSS for normal operation. GND 23, 24, 25 Logic ground (not for power return or analog reference). Tie to VSS. 2, 4, 30, 35, NC No connect (DO NOT CONNECT) externally. Failure to leave NC pins open can cause faulty operation. 37 SCLK 27 Serial-communication clock input used for EEPROM programming SDATA 26 Serial-communication data input/output used for EEPROM programming (open-drain) SENSE(+) 10 Current-sense input SENSE( –) 9 Current-sense input TS 13 Temperature sensing input VC1 32 Sense-voltage input terminal for most-positive cell VC2 33 Sense-voltage input terminal for second-most-positive cell VC3 34 Sense-voltage input terminal for third-most-positive cell VC4 36 Sense-voltage input terminal for fourth-most-positive cell VC5 38 Sense-voltage input terminal for fifth-most-positive cell VC6 1 Sense-voltage input terminal for sixth-most-positive cell VC7 3 Sense-voltage input terminal for seventh-most-positive cell VC8 5 Sense-voltage input terminal for eighth-most-positive cell VC9 6 Sense-voltage input terminal for ninth-most-positive cell VC10 7 Sense-voltage input terminal for tenthmost-positive (most-negative) cell VC11 8 Most-negative cell( –) terminal (BAT–) VREG 12 Integrated 3.3-V regulator output VSS1 29 Analog ground (substrate reference) VSS2 11 Analog ground (substrate reference) VTSB 15 Thermistor bias supply (sourced from VREG) Zero Delay test mode pin. Enables serial communications interface and minimizes protection delay times ZEDE 22 when connected to logic high. Connect to VSS for normal operation. A strong connection is recommended. 2 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): bq77910 |
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