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SN75DP130 Datasheet(PDF) 7 Page - Texas Instruments |
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SN75DP130 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 31 page SN75DP130 www.ti.com SLLSE57 – APRIL 2011 POWER DISSIPATION PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT SN75DP130SS; 4 DP Lanes. 468 828 mW PN Device power under normal operation SN75DP130DS; 4 DP Lanes. 172 304 mW SN75DP130SS; 4 DP Lanes. 14.4 mW PSD Shutdown mode power dissipation SN75DP130DS; 4 DP Lanes. 7.2 mW SN75DP130SS; 4 DP Lanes. 14.4 mW PSBY Standby mode power dissipation SN75DP130DS; 4 DP Lanes. 7.2 mW SN75DP130SS; 4 DP Lanes. 54 mW PD3 D3 power down mode dissipation SN75DP130DS; 4 DP Lanes. 46 mW SN75DP130SS; 4 DP Lanes. 126 180 mW POD Output disable (squelch) mode current SN75DP130DS; 4 DP Lanes. 58 88 mW (1) Test conditions correspond to Power Supply test conditions in Electrical Characteristics RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V VDDD Digital core and Main Link supply voltage 0.97 1.05 1.2 V TA Operating free-air temperature 0 85 °C TCASE Case temperature 103.1 °C VIH(HPD) High-level input voltage HPD_SNK 1.9 5.5 V VIH High-level input voltage for device control signals 1.9 3.6 V VIL Low-level input voltage for device control signals 0 0.8 V MAIN LINK TERMINALS VID Peak-to-peak input differential voltage; RBR, HBR, HBR2 0.30 1.40 Vpp dR Data rate 5.4 Gbps CAC AC coupling capacitance (each input and each output line) 75 200 nF Rtdiff Differential output termination resistance 80 100 120 Ω VOterm Output termination voltage (AC coupled) 0 2 V When used as re-driver in DP source 20 Intra-pair skew at tSK(in HBR2) ps the input at 5.4Gbps When used as receiver equalizer in DP sink 100 tSK(in HBR) Intra-pair skew at the input at 2.7Gbps 100 ps tSK(in RBR) Intra-pair skew at the input at 1.62Gbps 300 ps AUX CHANNEL DATA TERMINALS AUX_SRCp and AUX_SNKp in DP mode -0.5 0.3 0.4 VI-DC DC input voltage AUX_SRCn and AUX_SNKn in DP mode 2.0 3.0 3.6 V AUX_SRCp/n and AUX_SNKp/n in TMDS mode -0.5 3.6 VID Differential input voltage amplitude (DP mode only) 300 1400 mVPP dR(AUX) Data rate (before Manchester encoding) 0.8 1 1.2 Mbps dR(FAUX) Data rate Fast AUX (300ppm frequency tolerance) 720 Mbps tjccin_adj Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) 0.05 UI tjccin Cycle-to-cycle AUX input jitter within one cycle (DP mode only) 0.1 UI CAC AUX AC coupling capacitance (DP mode only) 75 200 nF AUX source common mode voltage (only applies to DP mode) VsrcCMM 0 2000 mV CAD = VIL; measured on AUX source and sink before AC coupling caps DDC AND I2C TERMINALS VI Input voltage -0.5 3.6 V dR Data rate 100 kbps VIH High-level input voltage 0.7VCC V VIL Low-level input voltage 0.3VCC V Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN75DP130 |
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