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TLK10002 Datasheet(PDF) 3 Page - Texas Instruments |
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TLK10002 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 73 page HSTXAP/N INA0P/N Ch annel A Low Speed Side SERDES HSRXAP/N 10 10 10 10 32 16 Pattern Generator 16 16 High Speed Side SERDES 20 16 20 10 10 10 10 32 LS PRBS Verifier LS PRBS Generator HS PRBS Generator HS PRBS Verifier MDIO Interface JTAG TMS TDO TRST_N TCK TDI INA1P/N INA2P/N INA3P/N OUTA0P/N OUTA1P/N OUTA2P/N OUTA3P/N LS_OK_OUT_A LS_OK_IN_A PDTRXA_N VDDRA_LS REFCLK0P/N REFCLK1P/N REFCLKA_SEL RESET_N PRTAD [4:0] MDC MDIO TESTEN PRBSEN PRBS_PASS CLKOUTAP/N LOSA VDDRA_HS VDDA VDDT VDDD DVDD VDDO VSS TX FIFO RX FIFO Pattern Verifier TLK10002 www.ti.com SLLSE75 – MAY 2011 BLOCK DIAGRAM A simplified block diagram of the TLK10002 device is shown in Figure 1 for Channel A which is identical to Channel B. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks carries out all the logic functions including channel synchronization, lane alignment, 8B/10B encoding/decoding, as well as test pattern generation and verification. The TLK10002 provides a management data input/output (MDIO) interface as well as a JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10002 pin functions is provided in Table 1. Figure 1. Simplified Block Diagram of the TLK10002 PACKAGE For the TLK10002, a 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used. The device pin-out is as shown in Figure 2 and is described in detail in Table 1 and Table 2. Copyright © 2011, Texas Instruments Incorporated 3 |
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