TPS54478

SLVSAS2

– JUNE 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE

PART NUMBER

–40°C to 150°C

3

× 3 mm QFN

TPS54478RTE

(1)

For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

UNIT

VIN

–0.3 to 7

EN

–0.3 to 7

BOOT

PH + 7

VSENSE

–0.3 to 3

Input voltage

V

COMP

–0.3 to 3

PWRGD

–0.3 to 7

SS/TR

–0.3 to 3

RT/CLK

–0.3 to 3.3

BOOT-PH

7

Output voltage

PH

–0.6 to 7

V

PH 10 ns Transient

–2 to 10

EN

100

Source current

µA

RT/CLK

100

COMP

100

µA

Sink current

PWRGD

10

mA

SS/TR

100

µA

2

kV

Electrostatic discharge (Charged Devic Model) QSS 009-147 (JESD22-C101B.01)

500

V

–40 to 150

°C

Temperature

–65 to 150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL

SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The human body model is a 100-pF capacitor discharged through a 1.5-k

Ω resistor into each pin. The machine model is a 200-pF

capacitor discharged directly into each pin.

2

Copyright

© 2011, Texas Instruments Incorporated