5

FN6666.5

April 7, 2011

Functional Pin Description

PIN

NAME

FUNCTION

1

PGOOD

Open-drain power-good status outputs. Connect to VCC through a 100k resistor. Output will be high when all outputs are

within regulation with no faults detected.

2

FSET2

Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. The pin output is

a pulsed current and requires a decoupling capacitor to average the signal.

3

FCCM

Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full

discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.

4

VCC

Analog power supply input for reference voltages and currents. Bypass to ground with a 1µF ceramic capacitor near the IC.

5

LDO3EN

Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.

6

FSET1

Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. The pin output is

a pulsed current and requires a decoupling capacitor to average the signal.

7

FB1

SMPS1 feedback input used for output voltage programming and regulation.

8

VOUT1

SMPS1 output voltage sense input. Used for soft-discharge.

9

ISEN1

10

OCSET1

Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS1.

11

EN1

Logic input to enable and disable SMPS1. A logic high will immediately enable SMPS1. Floating this pin will enable

SMPS1 only after SMPS2 has been enabled and achieved regulation. A logic low disables SMPS1.

12

PHASE1

SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS

source, the synchronous NMOS drain, and the output inductor for SMPS1.

13

UGATE1

High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.

14

BOOT1

SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to SMPS1 PHASE with a ceramic capacitor of 0.22µF.

15

LGATE1

Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.

16

LDO3

3.3V linear regulator output, capable of providing 100mA continuous current. Bypass to ground with a 4.7µF ceramic capacitor.

17

VIN

Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.

18

PVCC

5V power source for SMPS gate drive current. Bypass to ground with a 4.7µF ceramic capacitor.

19

PGND

Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.

20

LGATE2

Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.

21

BOOT2

SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to SMPS2 PHASE with a ceramic capacitor of 0.22µF.

22

UGATE2

High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.

23

PHASE2

SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS

source, the synchronous NMOS drain, and the output inductor for SMPS2.

24

EN2

Logic input to enable and disable SMPS2. A logic high will immediately enable SMPS2. Floating this pin will enable

SMPS2 only after SMPS1 has been enabled and achieved regulation. A logic low disables SMPS2.

25

OCSET2

Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS2.

26

ISEN2

27

VOUT2

SMPS2 output voltage sense input. Used for soft-discharge and switchover for PVCC 5V LDO.

28

FB2

SMPS2 feedback input used for output voltage programming and regulation.

Bottom

Pad

GND

Analog ground for analog and logic signals.

ISL62391, ISL62392, ISL62391C, ISL62392C