ISL95210

3

FN6938.2

June 2, 2011

Pin Configuration

ISL95210

(32 LD QFN)

TOP VIEW

1

2

34

5

6

78

910

27

26

25

24

23

22

21

20

19

18

16

15

14

13

12

11

28

29

30

31

32

17

MSEL

MPCT

VCC

VOUT

AGND

VSEL0

DNC

PGND

PGND

PVCC

PVCC

VIN

PGND

Functional Pin Descriptions

PIN

NAME

FUNCTION

Thermal Pad

PGND

Power ground. This thermal pad provides a return path for power stage and switching currents as well as a thermal path

for removing heat from the IC into the board. Place thermal vias in the pad to the PGND plane.

1

FCCM

Logic input for operating mode selection. Connect this pin to VCC for CCM regulation only. Connect this pin to AGND to allow

discontinuous conduction mode for light-load efficiency. Float this pin for audio mode light-load switching.

2

FSET

Tri-state digital input for programming the regulator switching frequency. Pull this pin to VCC for 800kHz switching. Pull this

pin to GND for 400kHz switching. Leave this pin floating for 533kHz switching.

3

EN

Logic input for enabling and disabling output voltage regulation. Pull this pin to VCC to begin regulation. Pull this pin to AGND

to disable regulation.

4, 5, 6, 7, 8, 9,

10

PHASE

Power stage switching node for output voltage regulation. Connect to the output inductor. All PHASE pins must be shorted

on the printed circuit board.

11

DNC

No connect. This pin must be left floating under all conditions.

12, 13, 19, 20,

21, 22, 23

PGND

Power ground. This pin provides a return path for power stage and switching currents. All PGND pins must be shorted on

the printed circuit board.

14, 15

PVCC

Power input for the integrated MOSFET gate drivers. Connect to a +5V supply. Both PVCC pins must be shorted on the

printed circuit board.

16, 17, 18

VIN

Power input for buck regulation stage. Bypass to PGND with one 10µF or 22µF ceramic capacitor. Connect to a +3.3V to

+5V supply. All VIN pins must be shorted on the printed circuit board.

24

PG_IN

Input voltage for the power-good CMOS output. Connect this pin to the desired PGOOD output high level.

25

PG_OUT

Active CMOS output for power-good indication. High state is indicated when the output voltage is in regulation, and output

is logic low otherwise. Logic high level is set by the voltage on the PG_IN pin.

26

VSEL1

DAC logic MSB input. Used to program preset output voltages of 0.60V, 0.75V, 0.90V, 1.00V, 1.05V, 1.10V, 1.20V, 1.50V,

and 1.80V.

27

VSEL0

DAC logic LSB input. Used to program preset output voltages of 0.60V, 0.75V, 0.90V, 1.00V, 1.05V, 1.10V, 1.20V, 1.50V,

and 1.80V.

28

AGND

Ground reference for analog signals. Connect this pin to the ground plane.

29

VOUT

Sense point for output voltage regulation and output soft-discharge. Connect to the desired regulation point.