STK15C88

Document Number: 001-50593 Rev. *C

Page 10 of 17

SRAM Write Cycle

Parameter

Description

25 ns

45 ns

Unit

Min

Max

Min

Max

Cypress

Parameter

Alt

Write Cycle Time

25

45

ns

Write Pulse Width

20

30

ns

Chip Enable To End of Write

20

30

ns

Data Setup to End of Write

10

15

ns

Data Hold After End of Write

0

0

ns

Address Setup to End of Write

20

30

ns

Address Setup to Start of Write

0

0

ns

Address Hold After End of Write

0

0

ns

[7,8]

Write Enable to Output Disable

10

15

ns

[7]

Output Active After End of Write

5

5

ns

Switching Waveforms

Figure 7. SRAM Write Cycle 1: WE Controlled [8]

Figure 8. SRAM Write Cycle 2: CE Controlled [8]

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.

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