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STK14C88-NF45ITR Datasheet(PDF) 8 Page - Cypress Semiconductor |
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STK14C88-NF45ITR Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 20 page STK14C88 Document Number: 001-52038 Rev. *C Page 8 of 20 Hardware Mode Selection E W HSB A13 - A0 (hex) Mode I/O Power Notes H X H X Not Selected Output High Z Standby – L H H X Read SRAM Output Data Active 19 L L H X Write SRAM Input Data Active – X X L X Nonvolatile STORE Output High Z lCC2 12 Hardware STORE Cycle No. Symbols Parameter STK14C88 Units Notes Standard Alternate Min Max 22 tSTORE tHLHZ STORE Cycle Duration – 10 ms 13 23 tDELAY tHLQZ Time Allowed to Complete SRAM Cycle 1 – s13 24 tRECOVER tHHQX Hardware STORE High to Inhibit Off – 700 ns 13, 14 25 tHLHX Hardware STORE Pulse Width 15 – ns – 26 tHLBL Hardware STORE Low to STORE Busy – 300 ns – Figure 8. Hardware STORE Cycle DATA VALID HSB (IN) DATA VALID 25 tHLHX 23 tDELAY 22 tSTORE 24 tRECOVER HIGH IMPEDANCE 27 tHLBL HIGH IMPEDANCE DQ (DATA OUT) HSB (OUT) Notes 12. HSB STORE operation occurs only if an SRAM write is done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby mode, inhibiting all operations until HSB rises 13. E and G low, W high for output behavior. 14. tRECOVER is only applicable after tSTORE is complete. [+] Feedback |
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