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71M6515H Datasheet(PDF) 10 Page - Teridian Semiconductor Corporation

Part # 71M6515H
Description  Up to 10ppmC precision ultra-stable voltage reference Digital temperature compensation
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Manufacturer  TERIDIAN [Teridian Semiconductor Corporation]
Direct Link  http://www.teridian.com
Logo TERIDIAN - Teridian Semiconductor Corporation

71M6515H Datasheet(HTML) 10 Page - Teridian Semiconductor Corporation

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71M6515H
Energy Meter IC
DATA SHEET
JULY 2011
Page: 10 of 60
© 2005
−2011 Teridian Semiconductor Corporation
1.6
A Maxim Integrated Products Brand
Analog Pin Description
Name
Pin
No.
Type
Circuit
Description
IA,
IB,
IC
56
55
54
I
6
Line Current Sense Inputs: Voltage inputs to the internal A/D converter. Typically,
they are connected to the output of a current transformer. The input is referenced
to V3P3A. Unused pins must be tied to V3P3A.
VA,
VB,
VC
53
52
51
I
6
Line Voltage Sense Inputs: Voltage inputs to the internal A/D converter. Typically,
they are connected to the output of a resistor divider. The input is referenced to
V3P3A. Unused pins must be tied to V3P3A.
VFLT
59
I
7
Power Fault Input. This pin must be tied to V3P3A.
VX
58
I
6
Auxiliary input (not used). This pin should be tied to VREF.
VREF
57
I/O
9
Voltage Reference for the ADC.
XIN,
XOUT
61
63
I
8
Crystal Inputs: A 32768Hz crystal should be connected across these pins.
Typically, a 15pF capacitor is also connected from each pin to GNDA. See the
datasheet of the crystal manufacturer for details.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output
The circuit number denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
Digital Pin Description
Unless otherwise indicated, all inputs and outputs are standard CMOS. Inputs do NOT have internal pull-ups or pull-downs.
Name
Pin
No.
Type
Circuit
Description
CKTEST
6
I/O
4
Clock PLL output. Can be enabled and disabled by CKOUT_DSB (see
Status Mask).
D0
D1
D2
D3
D4
D5
D6
D7
42
21
22
23
37
38
39
33
I/O
3, 4
Input/output pins 0 through 7. These pins must be terminated to
V3P3D or ground if configured as input pins.
D0 through D7 are high impedance after reset or power-up and are
configured as outputs and driven low 140ms after RESETZ goes
high.
PULSE4
15
O
4
The fourth pulse generator output
PULSE3
14
O
4
The third pulse generator output
PULSE_INIT
40
I
3
The pulse output initial power-up voltage (0: 0V, 1: 3.3V), default is 1.
This pin must be terminated to V3P3D or ground.
BAUD_RATE
16
I
3
The UART baud rate (1: 38.4kbd, 0: 19.2kbd). This pin must be
terminated to V3P3D or ground.
IRQZ
41
O
4
Interrupt output, low active. A falling edge indicates the end of a
measurement frame, as well as alarms. Rises when status word is
read.
MUXSYNC
25
O
4
Internal signal. MUXSYNC falls at the beginning of each conversion
cycle (multiplexer frame).
RESETZ
47
I
1
Chip reset: Input pin with internal pull-up resistor, used to reset the chip
into a known state. For normal operation, this pin is set to 1. To reset
the chip, this pin is driven to 0 for 5 microseconds. No external reset
circuitry is necessary for power-up reset.


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