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PCA9621D Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCA9621D Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 18 page PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 9 March 2011 5 of 18 NXP Semiconductors PCA9621 65 mA 8-bit 2-wire bus output port 7.6 A0, A1, A2 — address lines The slave address of the PCA9621 is shown in Figure 4. The address pins (A2, A1, A0) must be driven to a HIGH or LOW level—they are not internally pulled to a default state. The read/write bit must be set LOW to enable a write to the Control register, or HIGH to read from the Control register. 7.7 Control register The Control register of the PCA9621 is shown in Figure 5. Each of the four output ports can be activated independently by setting the appropriate bit in the Control register. A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled (high-impedance). The default reset condition of the register is all zeros, all ports high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking). Example: Programming C1h (1100 0001b) into the Control register results in ports P0, P6 and P7 being ON (sinking) and the remaining ports being OFF (high-impedance). Fig 4. Slave address 002aaf383 1 1 0 0 A2 A1 A0 R/W fixed externally selectable read = 1 write = 0 1 = ON (sinking) 0 = OFF (high-impedance) Fig 5. Control register 002aaf384 P7 P6 P5 P4 P3 P2 P1 P0 MSB LSB |
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