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TPS65835 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS65835 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 62 page  TPS65835 SLVSAF6 – JUNE 2011 www.ti.com Table 1-1. Pin Descriptions (continued) PIN NAME I/O PIN NO. DESCRIPTION P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output UCB0CLK/ USCI_B0 clock input/output UCA0STE/ I/O 39 USCI_A0 slave transmit enable A5/ ADC10 analog input A5 CA5/ Comparator_A+, CA5 input TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin TA0.1/ Timer0_A, compare: Out1 output A6/ ADC10 analog input A6 CA6/ I/O 13 Comparator_A+, CA6 input UCB0SOMI/ USCI_B0 slave out/master in SPI mode UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode TDI/TCLK JTAG test data input or test clock input during programming and test P1.7/ General-purpose digital I/O pin A7/ ADC10 analog input A7 CA7/ Comparator_A+, CA7 input CAOUT/ I/O 16 Comparator_A+, output UCB0SIMO/ USCI_B0 slave in/master out in SPI mode UCB0SDA/ USCI_B0 SDA I2C data in I2C mode TDO/TDI JTAG test data output terminal or test data input during programming and test(2) P2.1/ General-purpose digital I/O pin I/O 1 TA1.1 Timer1_A, capture: CCI1A input, compare: Out1 output P2.2/ General-purpose digital I/O pin I/O 2 TA1.1 Timer1_A, capture: CCI1B input, compare: Out1 output P2.6/ General-purpose digital I/O pin XIN/ I/O 24 XIN, Input terminal of crystal oscillator TA0.1 TA0.1, Timer0_A, compare: Out1 output P2.7/ General-purpose digital I/O pin I/O 21 XOUT Output terminal of crystal oscillator(3)) P3.3/ General-purpose digital I/O pin I/O 3 TA1.2 Timer1_A, compare: Out2 output P3.5/ General-purpose digital I/O pin I/O 9 TA0.1 Timer0_A, compare: Out0 output nRST/ Reset NMI/ I/O 17 Nonmaskable interrupt input SBWTDIO Spy-Bi-Wire test data input/output during programming and test TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. I 20 SBWTCK Spy-Bi-Wire test clock input during programming and test DVSS - 25 MSP430 Ground reference(4) MISC. AND PACKAGE There is an internal electrical connection between the exposed thermal pad and the AGND ground pin of the device. The thermal pad must be connected to the same potential as the AGND pin on Thermal PAD - 41 the printed circuit board. Do not use the thermal pad as the primary ground input for the device. AGND pin must be connected to ground at all times. All N/C pins are not connected internally (package to die). They should be connected to the main N/C - 10, 40 system ground. (2) TDO or TDI is selected via JTAG instruction. (3) If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. (4) MSP430 ground and grounds for PMIC (Power Management Core) are connected internally. Table 1-2. Pin Absolute Maximum Ratings PIN VALUE / UNIT Input voltage range on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP, -0.3 V to 7.0 V LCRN, AGND, DGND, PGNDBST, and MSP430 Core pins) with respect to AGND VIN with respect to AGND -0.3 V to 28.0 V BST_OUT, BST_SW with respect to PGNDBST -0.3 V to 18.0 V BST_FB with respect to PGNDBST, VLDO with respect to DGND -0.3 V to 3.6 V MSP430 Core Pins -0.3 V to 4.1 V 10 INTRODUCTION Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS65835 |
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