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TMS320C28346ZFEQ Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C28346ZFEQ Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 170 page  TMS320C28346, TMS320C28345, TMS320C28344 TMS320C28343, TMS320C28342, TMS320C28341 SPRS516B – MARCH 2009 – REVISED JULY 2010 www.ti.com Contents 1 TMS320C2834x ( Delfino™) MCUs ....................................................................................... 11 1.1 Overview .................................................................................................................... 11 1.2 Features .................................................................................................................... 11 1.3 Getting Started ............................................................................................................. 12 2 Introduction ...................................................................................................................... 13 2.1 Pin Assignments ........................................................................................................... 16 2.2 Signal Descriptions ........................................................................................................ 24 3 Functional Overview .......................................................................................................... 35 3.1 Memory Maps .............................................................................................................. 36 3.2 Brief Descriptions .......................................................................................................... 41 3.2.1 C28x CPU ....................................................................................................... 41 3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 41 3.2.3 Peripheral Bus .................................................................................................. 41 3.2.4 Real-Time JTAG and Analysis ................................................................................ 42 3.2.5 External Interface (XINTF) .................................................................................... 42 3.2.6 M0, M1 SARAMs ............................................................................................... 42 3.2.7 L0, L1, L2, L3, L4, L5, L6, L7 , H0, H1, H2, H3, H4, H5 SARAMs ....................................... 42 3.2.8 Boot ROM ....................................................................................................... 43 3.2.9 Security .......................................................................................................... 43 3.2.10 Peripheral Interrupt Expansion (PIE) Block ................................................................. 44 3.2.11 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 44 3.2.12 Oscillator and PLL .............................................................................................. 44 3.2.13 Watchdog ........................................................................................................ 44 3.2.14 Peripheral Clocking ............................................................................................. 44 3.2.15 Low-Power Modes .............................................................................................. 44 3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 45 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 45 3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 45 3.2.19 Control Peripherals ............................................................................................. 46 3.2.20 Serial Port Peripherals ......................................................................................... 46 3.3 Register Map ............................................................................................................... 47 3.4 Device Emulation Registers .............................................................................................. 48 3.5 Interrupts .................................................................................................................... 49 3.5.1 External Interrupts .............................................................................................. 53 3.6 System Control ............................................................................................................ 54 3.6.1 OSC and PLL Block ............................................................................................ 55 3.6.1.1 External Reference Oscillator Clock Option .................................................... 57 3.6.1.2 PLL-Based Clock Module ......................................................................... 58 3.6.1.3 Loss of Input Clock ................................................................................ 59 3.6.2 Watchdog Block ................................................................................................. 60 3.7 Low-Power Modes Block ................................................................................................. 61 4 Peripherals ....................................................................................................................... 62 4.1 DMA Overview ............................................................................................................. 62 4.2 32-Bit CPU-Timers 0/1/2 ................................................................................................. 64 4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6 /7/8/9) ................................................................. 66 2 Contents Copyright © 2009–2010, Texas Instruments Incorporated |
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