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TMS320F28021 Datasheet(PDF) 10 Page - Texas Instruments

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Part # TMS320F28021
Description  Piccolo Microcontrollers
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F28021 Datasheet(HTML) 10 Page - Texas Instruments

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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523F – NOVEMBER 2008 – REVISED DECEMBER 2010
www.ti.com
Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL
I/O/Z
DESCRIPTION
PT
DA
NAME
PIN #
PIN #
CPU AND I/O POWER
VDDA
11
22
Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin.
VSSA
Analog Ground Pin
12
23
I
VREFLO
ADC Low Reference (always tied to ground)
VDD
32
1
CPU and Logic Digital Power Pins – no supply source needed when using internal
VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may be used, but could impact
VDD
43
11
supply-rail ramp-up time.
Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled. Tie
VDDIO
35
4
with a 2.2-µF capacitor (typical) close to the pin.
VSS
33
2
Digital Ground Pins
VSS
44
12
VOLTAGE REGULATOR CONTROL SIGNAL
Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator
VREGENZ
34
3
I
(VREG), pull high to disable VREG.
GPIO AND PERIPHERAL SIGNALS (1)
GPIO0
29
37
I/O/Z
General purpose input/output 0
EPWM1A
O
Enhanced PWM1 Output A and HRPWM channel
GPIO1
28
36
I/O/Z
General purpose input/output 1
EPWM1B
O
Enhanced PWM1 Output B
COMP1OUT
O
Direct output of Comparator 1
GPIO2
37
5
I/O/Z
General purpose input/output 2
EPWM2A
O
Enhanced PWM2 Output A and HRPWM channel
GPIO3
38
6
I/O/Z
General purpose input/output 3
EPWM2B
O
Enhanced PWM2 Output B
COMP2OUT
O
Direct output of Comparator 2 (available in 48-pin device only)
GPIO4
39
7
I/O/Z
General purpose input/output 4
EPWM3A
O
Enhanced PWM3 output A and HRPWM channel
GPIO5
40
8
I/O/Z
General purpose input/output 5
EPWM3B
O
Enhanced PWM3 output B
ECAP1
I/O
Enhanced Capture input/output 1
GPIO6
41
9
I/O/Z
General purpose input/output 6
EPWM4A
O
Enhanced PWM4 output A and HRPWM channel
EPWMSYNCI
I
External ePWM sync pulse input
EPWMSYNCO
O
External ePWM sync pulse output
(1)
The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the
TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for details.
10
Introduction
Copyright © 2008–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200


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