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TMS320F28020 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320F28020 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 130 page  TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022 TMS320F28021, TMS320F28020, TMS320F280200 www.ti.com SPRS523F – NOVEMBER 2008 – REVISED DECEMBER 2010 Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL I/O/Z DESCRIPTION PT DA NAME PIN # PIN # On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must X1 45 – I be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I) On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be X2 46 – O connected across X1 and X2. If X2 is not used, it must be left unconnected. (O) RESET Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 6.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external XRS 3 17 I/OD circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) ADC, COMPARATOR, ANALOG I/O ADCINA7 6 – I ADC Group A, Channel 7 input ADCINA6 I ADC Group A, Channel 6 input 4 18 AIO6 I/O Digital AIO 6 ADCINA4 I ADC Group A, Channel 4 input COMP2A 5 19 I Comparator Input 2A (available in 48-pin device only) AIO4 I/O Digital AIO 4 ADCINA3 7 – I ADC Group A, Channel 3 input ADCINA2 I ADC Group A, Channel 2 input COMP1A 9 20 I Comparator Input 1A AIO2 I/O Digital AIO 2 ADCINA1 8 – I ADC Group A, Channel 1 input ADC Group A, Channel 0 input ADCINA0 I 10 21 ADC External Reference – only used when in ADC external reference mode. See VREFHI I Section 4.1.1, ADC. ADCINB7 18 – I ADC Group B, Channel 7 input ADCINB6 I ADC Group B, Channel 6 input 17 26 AIO14 I/O Digital AIO 14 ADCINB4 I ADC Group B, Channel 4 input COMP2B 16 25 I Comparator Input 2B (available in 48-pin device only) AIO12 I/O Digital AIO12 ADCINB3 15 – I ADC Group B, Channel 3 input ADCINB2 I ADC Group B, Channel 2 input COMP1B 14 24 I Comparator Input 1B AIO10 I/O Digital AIO 10 ADCINB1 13 – I ADC Group B, Channel 1 input Copyright © 2008–2010, Texas Instruments Incorporated Introduction 9 Submit Documentation Feedback Product Folder Link(s): TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 |
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