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TMS320F28332ZJZQ Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320F28332ZJZQ Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 195 page  TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439I – JUNE 2007 – REVISED MARCH 2011 Digital Signal Controllers (DSCs) Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 1 TMS320F2833x, TMS320F2823x DSCs 1.1 Features 123 • High-Performance Static CMOS Technology • Enhanced Control Peripherals – Up to 150 MHz (6.67-ns Cycle Time) – Up to 18 PWM Outputs – 1.9-V/1.8 -V Core, 3.3-V I/O Design – Up to 6 HRPWM Outputs With 150 ps MEP Resolution • High-Performance 32-Bit CPU (TMS320C28x) – Up to 6 Event Capture Inputs – IEEE-754 Single-Precision Floating-Point Unit (FPU) (F2833x only) – Up to 2 Quadrature Encoder Interfaces – 16 x 16 and 32 x 32 MAC Operations – Up to 8 32-Bit/Nine 16-Bit Timers – 16 x 16 Dual MAC • Three 32-Bit CPU Timers – Harvard Bus Architecture • Serial Port Peripherals – Fast Interrupt Response and Processing – Up to 2 CAN Modules – Unified Memory Programming Model – Up to 3 SCI (UART) Modules – Code-Efficient (in C/C++ and Assembly) – Up to 2 McBSP Modules (Configurable as SPI) • Six-Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM) – One SPI Module • 16-Bit or 32-Bit External Interface (XINTF) – One Inter-Integrated-Circuit (I2C) Bus – Over 2M x 16 Address Reach • 12-Bit ADC, 16 Channels • On-Chip Memory – 80-ns Conversion Rate – F28335/F28235: 256K x 16 Flash, 34K x 16 – 2 x 8 Channel Input Multiplexer SARAM – Two Sample-and-Hold – F28334/F28234: 128K x 16 Flash, 34K x 16 – Single/Simultaneous Conversions SARAM – Internal or External Reference – F28332/F28232: 64K x 16 Flash, 26K x 16 • Up to 88 Individually Programmable, SARAM Multiplexed GPIO Pins With Input Filtering – 1K x 16 OTP ROM • JTAG Boundary Scan Support (1) • Boot ROM (8K x 16) • Advanced Emulation Features – With Software Boot Modes (via SCI, SPI, – Analysis and Breakpoint Functions CAN, I2C, McBSP, XINTF, and Parallel I/O) – Real-Time Debug via Hardware – Standard Math Tables • Development Support Includes • Clock and System Control – ANSI C/C++ Compiler/Assembler/Linker – Dynamic PLL Ratio Changes Supported – Code Composer Studio™ IDE – On-Chip Oscillator – DSP/BIOS™ – Watchdog Timer Module – Digital Motor Control and Digital Power • GPIO0 to GPIO63 Pins Can Be Connected to Software Libraries One of the Eight External Core Interrupts • Low-Power Modes and Power Savings • Peripheral Interrupt Expansion (PIE) Block That – IDLE, STANDBY, HALT Modes Supported Supports All 58 Peripheral Interrupts – Disable Individual Peripheral Clocks • 128-Bit Security Key/Lock – Protects Flash/OTP/RAM Blocks – Prevents Firmware Reverse Engineering (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 MicroStar BGA, Code Composer Studio, DSP/BIOS, TMS320C28x, Delfino, PowerPAD, TMS320C54x, TMS320C55x, C28x are trademarks of Texas Instruments. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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